RV_DM/USE_JTAG_INTERFACE Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 13.780s 10.099ms 0 1 0.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.040s 527.983us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.090s 438.621us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 44.640s 21.186ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.380s 813.032us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 2.650s 1.670ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 7.620s 5.843ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 30.240s 15.520ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 10.260s 20.463ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.110s 593.649us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.980s 158.423us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.720s 369.092us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.940s 167.727us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.830s 109.250us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.850s 826.189us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.610s 132.669us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.010s 194.653us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 2.110s 593.649us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.970s 155.393us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.830s 230.725us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.720s 369.092us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.800s 71.105us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.290s 379.354us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.680s 86.670us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 20.180s 1.983ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 24.030s 4.919ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.840s 111.648us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 24.030s 4.919ms 1 1 100.00
rv_dm_csr_rw 2.680s 86.670us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.530s 28.811us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.750s 135.420us 1 1 100.00
V1 TOTAL 25 27 92.59
V2 idcode rv_dm_smoke 13.780s 10.099ms 0 1 0.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.780s 173.098us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.600s 121.136us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.820s 241.648us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.310s 535.270us 1 1 100.00
V2 sba rv_dm_sba_tl_access 4.170s 3.600ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.770s 186.166us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 1.670s 51.193us 0 1 0.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 6.090s 14.963ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.390s 338.654us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 5.380s 2.122ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.920s 375.558us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.760s 104.697us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 12.390s 5.240ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.720s 22.366us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.840s 139.618us 1 1 100.00
V2 stress_all rv_dm_stress_all 3.550s 2.069ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.710s 52.214us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.740s 43.488us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.740s 43.488us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 24.030s 4.919ms 1 1 100.00
rv_dm_csr_hw_reset 2.290s 379.354us 1 1 100.00
rv_dm_csr_rw 2.680s 86.670us 1 1 100.00
rv_dm_same_csr_outstanding 6.030s 589.452us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 24.030s 4.919ms 1 1 100.00
rv_dm_csr_hw_reset 2.290s 379.354us 1 1 100.00
rv_dm_csr_rw 2.680s 86.670us 1 1 100.00
rv_dm_same_csr_outstanding 6.030s 589.452us 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 2.240s 329.309us 1 1 100.00
rv_dm_tl_intg_err 7.810s 3.801ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 7.810s 3.801ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 5.380s 2.122ms 1 1 100.00
rv_dm_debug_disabled 1.640s 166.409us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 5.380s 2.122ms 1 1 100.00
rv_dm_debug_disabled 1.640s 166.409us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 13.780s 10.099ms 0 1 0.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.250s 519.910us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.720s 90.922us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.720s 90.922us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.250s 519.910us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.660s 83.844us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 2.000s 24.831us 1 1 100.00
TOTAL 46 53 86.79

Failure Buckets