SPI_DEVICE/1R1W Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	56.230s	27.867ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.750s	23.874us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.310s	132.977us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.560s	2.701ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.600s	2.281ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.360s	102.165us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.310s	132.977us	1	1	100.00
		spi_device_csr_aliasing	16.600s	2.281ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.640s	10.791us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.000s	117.783us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.620s	18.462us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.680s	4.763us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.510s	6.789us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.130s	82.830us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.130s	82.830us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	7.820s	27.719ms	1	1	100.00
		spi_device_tpm_sts_read	1.930s	55.482us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	14.560s	7.213ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	13.230s	12.306ms	1	1	100.00
		spi_device_flash_all	1.557m	84.803ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.500s	1.480ms	1	1	100.00
		spi_device_flash_all	1.557m	84.803ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.500s	1.480ms	1	1	100.00
		spi_device_flash_all	1.557m	84.803ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.557m	84.803ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	6.310s	8.898ms	1	1	100.00
		spi_device_flash_all	1.557m	84.803ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	6.310s	8.898ms	1	1	100.00
		spi_device_flash_all	1.557m	84.803ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	6.310s	8.898ms	1	1	100.00
		spi_device_flash_all	1.557m	84.803ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	6.310s	8.898ms	1	1	100.00
		spi_device_flash_all	1.557m	84.803ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	6.310s	8.898ms	1	1	100.00
		spi_device_flash_all	1.557m	84.803ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.860s	5.404ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.110m	38.575ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.110m	38.575ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.110m	38.575ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	8.530s	1.160ms	1	1	100.00
		spi_device_read_buffer_direct	5.990s	2.472ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.110m	38.575ms	1	1	100.00
		spi_device_flash_all	1.557m	84.803ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.557m	84.803ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.557m	84.803ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.360s	315.461us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.360s	315.461us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	56.230s	27.867ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.877m	29.076ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.950s	91.541us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.660s	14.761us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.720s	40.298us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.740s	571.198us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.740s	571.198us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.750s	23.874us	1	1	100.00
		spi_device_csr_rw	2.310s	132.977us	1	1	100.00
		spi_device_csr_aliasing	16.600s	2.281ms	1	1	100.00
		spi_device_same_csr_outstanding	3.670s	479.985us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.750s	23.874us	1	1	100.00
		spi_device_csr_rw	2.310s	132.977us	1	1	100.00
		spi_device_csr_aliasing	16.600s	2.281ms	1	1	100.00
		spi_device_same_csr_outstanding	3.670s	479.985us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.060s	360.921us	1	1	100.00
		spi_device_tl_intg_err	9.770s	197.337us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.770s	197.337us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	49.300s	7.143ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.15979987716278058787656804362544524236758490993528454169484277928676322107900
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3021977 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[53])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3021977 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3021977 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[949])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.91489393280276542057033231082101562481229847045544738133646202023871897741828
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3991321 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb9b45c [101110011011010001011100] vs 0x0 [0])
        UVM_ERROR @   4052321 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x448b61 [10001001000101101100001] vs 0x0 [0])
        UVM_ERROR @   4139321 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8d6401 [100011010110010000000001] vs 0x0 [0])
        UVM_ERROR @   4232321 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbf1219 [101111110001001000011001] vs 0x0 [0])
        UVM_ERROR @   4257321 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa5a0a6 [101001011010000010100110] vs 0x0 [0])