SPI_DEVICE/2P Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 3.241m 383.546ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.970s 30.805us 1 1 100.00
V1 csr_rw spi_device_csr_rw 2.550s 76.575us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 19.240s 1.884ms 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 7.870s 1.232ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 2.470s 50.766us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.550s 76.575us 1 1 100.00
spi_device_csr_aliasing 7.870s 1.232ms 1 1 100.00
V1 mem_walk spi_device_mem_walk 1.900s 13.792us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.470s 64.250us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 1.680s 13.455us 1 1 100.00
V2 mem_parity spi_device_mem_parity 1.820s 66.974us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 1.560s 38.230us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 4.840s 112.269us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 4.840s 112.269us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 5.680s 1.630ms 1 1 100.00
spi_device_tpm_sts_read 1.730s 108.669us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 2.440s 350.962us 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 6.350s 1.002ms 1 1 100.00
spi_device_flash_all 28.250s 8.805ms 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 14.490s 10.707ms 1 1 100.00
spi_device_flash_all 28.250s 8.805ms 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 14.490s 10.707ms 1 1 100.00
spi_device_flash_all 28.250s 8.805ms 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 28.250s 8.805ms 1 1 100.00
V2 cmd_read_status spi_device_intercept 4.080s 700.708us 1 1 100.00
spi_device_flash_all 28.250s 8.805ms 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 4.080s 700.708us 1 1 100.00
spi_device_flash_all 28.250s 8.805ms 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 4.080s 700.708us 1 1 100.00
spi_device_flash_all 28.250s 8.805ms 1 1 100.00
V2 cmd_fast_read spi_device_intercept 4.080s 700.708us 1 1 100.00
spi_device_flash_all 28.250s 8.805ms 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 4.080s 700.708us 1 1 100.00
spi_device_flash_all 28.250s 8.805ms 1 1 100.00
V2 flash_cmd_upload spi_device_upload 5.730s 797.035us 1 1 100.00
V2 mailbox_command spi_device_mailbox 2.660s 103.214us 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 2.660s 103.214us 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 2.660s 103.214us 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 6.620s 249.728us 1 1 100.00
spi_device_read_buffer_direct 4.490s 5.433ms 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 2.660s 103.214us 1 1 100.00
spi_device_flash_all 28.250s 8.805ms 1 1 100.00
V2 quad_spi spi_device_flash_all 28.250s 8.805ms 1 1 100.00
V2 dual_spi spi_device_flash_all 28.250s 8.805ms 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 8.410s 2.080ms 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 8.410s 2.080ms 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 3.241m 383.546ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 2.989m 43.416ms 1 1 100.00
V2 stress_all spi_device_stress_all 5.117m 246.130ms 1 1 100.00
V2 alert_test spi_device_alert_test 1.590s 14.995us 1 1 100.00
V2 intr_test spi_device_intr_test 1.740s 21.655us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 2.860s 31.101us 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 2.860s 31.101us 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.970s 30.805us 1 1 100.00
spi_device_csr_rw 2.550s 76.575us 1 1 100.00
spi_device_csr_aliasing 7.870s 1.232ms 1 1 100.00
spi_device_same_csr_outstanding 4.990s 184.079us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.970s 30.805us 1 1 100.00
spi_device_csr_rw 2.550s 76.575us 1 1 100.00
spi_device_csr_aliasing 7.870s 1.232ms 1 1 100.00
spi_device_same_csr_outstanding 4.990s 184.079us 1 1 100.00
V2 TOTAL 22 22 100.00
V2S tl_intg_err spi_device_sec_cm 1.990s 259.124us 1 1 100.00
spi_device_tl_intg_err 10.580s 642.913us 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 10.580s 642.913us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 53.540s 6.692ms 1 1 100.00
TOTAL 33 33 100.00