SPI_HOST Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	33.000s	2.345ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	62.361us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	18.626us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	38.011us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	21.093us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	25.773us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	18.626us	1	1	100.00
		spi_host_csr_aliasing	4.000s	21.093us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	15.073us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	16.379us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	6.000s	43.671us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	128.333us	1	1	100.00
		spi_host_error_cmd	4.000s	20.835us	1	1	100.00
		spi_host_event	24.000s	746.448us	1	1	100.00
V2	clock_rate	spi_host_speed	13.000s	141.151us	1	1	100.00
V2	speed	spi_host_speed	13.000s	141.151us	1	1	100.00
V2	chip_select_timing	spi_host_speed	13.000s	141.151us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	4.000s	36.417us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	33.227us	1	1	100.00
V2	cpol_cpha	spi_host_speed	13.000s	141.151us	1	1	100.00
V2	full_cycle	spi_host_speed	13.000s	141.151us	1	1	100.00
V2	duplex	spi_host_smoke	33.000s	2.345ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	33.000s	2.345ms	1	1	100.00
V2	stress_all	spi_host_stress_all	18.000s	453.024us	1	1	100.00
V2	spien	spi_host_spien	4.000s	311.837us	1	1	100.00
V2	stall	spi_host_status_stall	53.000s	1.512ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	453.290us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	128.333us	1	1	100.00
V2	alert_test	spi_host_alert_test	3.000s	16.354us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	18.049us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	105.436us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	105.436us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	62.361us	1	1	100.00
		spi_host_csr_rw	4.000s	18.626us	1	1	100.00
		spi_host_csr_aliasing	4.000s	21.093us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	68.577us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	62.361us	1	1	100.00
		spi_host_csr_rw	4.000s	18.626us	1	1	100.00
		spi_host_csr_aliasing	4.000s	21.093us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	68.577us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	262.577us	1	1	100.00
		spi_host_sec_cm	4.000s	267.206us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	262.577us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	4.617m	14.404ms	1	1	100.00
		TOTAL			26	26	100.00