SRAM_CTRL/MAIN Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	32.770s	1.703ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.650s	78.683us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.970s	48.358us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.060s	147.689us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.000s	17.141us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.600s	350.148us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.970s	48.358us	1	1	100.00
		sram_ctrl_csr_aliasing	2.000s	17.141us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.862m	14.086ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.784m	12.216ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.377m	47.369ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.187m	4.677ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	20.971m	77.705ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.252m	39.050ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	45.760s	70.790ms	1	1	100.00
V2	executable	sram_ctrl_executable	6.897m	16.152ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	31.350s	7.174ms	1	1	100.00
		sram_ctrl_partial_access_b2b	7.134m	386.970ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	18.740s	11.951ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	44.840s	3.119ms	1	1	100.00
		sram_ctrl_throughput_w_readback	1.071m	930.102us	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.318m	30.116ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.090s	350.620us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	22.238m	170.344ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.870s	15.563us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.310s	161.943us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.310s	161.943us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.650s	78.683us	1	1	100.00
		sram_ctrl_csr_rw	1.970s	48.358us	1	1	100.00
		sram_ctrl_csr_aliasing	2.000s	17.141us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.970s	39.692us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.650s	78.683us	1	1	100.00
		sram_ctrl_csr_rw	1.970s	48.358us	1	1	100.00
		sram_ctrl_csr_aliasing	2.000s	17.141us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.970s	39.692us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	33.050s	7.549ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.660s	1.970us	0	1	0.00
		sram_ctrl_tl_intg_err	2.750s	100.998us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.660s	1.970us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.750s	100.998us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.318m	30.116ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.318m	30.116ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.970s	48.358us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.897m	16.152ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.897m	16.152ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.897m	16.152ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	45.760s	70.790ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.770s	1.366ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	33.050s	7.549ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.670s	691.389us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	32.770s	1.703ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	32.770s	1.703ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.897m	16.152ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.660s	1.970us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	45.760s	70.790ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.660s	1.970us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.660s	1.970us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	32.770s	1.703ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.660s	1.970us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	14.060s	2.014ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.80499974133343177405164509665468822784789141415951952440583552883006655342753
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 691388979 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x65) != exp (0x38)
        UVM_INFO @ 691388979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.94573902132195899795854433242992348147704092152500213158139519822149374181861
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   1969636 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   1969636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---