SRAM_CTRL/RET Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	6.770s	207.699us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.480s	33.137us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.630s	35.501us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.960s	101.111us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.530s	22.955us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.810s	57.283us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.630s	35.501us	1	1	100.00
		sram_ctrl_csr_aliasing	1.530s	22.955us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.030s	299.366us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.860s	110.933us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.279m	33.294ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.825m	7.224ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	15.560s	1.370ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.881m	48.242ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.470s	601.503us	1	1	100.00
V2	executable	sram_ctrl_executable	5.727m	17.811ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	1.740s	42.342us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.144m	51.798ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	33.230s	233.234us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	45.320s	155.995us	1	1	100.00
		sram_ctrl_throughput_w_readback	42.490s	582.689us	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.131m	24.239ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.620s	28.876us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	27.118m	204.075ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.510s	14.386us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.270s	66.975us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.270s	66.975us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.480s	33.137us	1	1	100.00
		sram_ctrl_csr_rw	1.630s	35.501us	1	1	100.00
		sram_ctrl_csr_aliasing	1.530s	22.955us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.590s	61.521us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.480s	33.137us	1	1	100.00
		sram_ctrl_csr_rw	1.630s	35.501us	1	1	100.00
		sram_ctrl_csr_aliasing	1.530s	22.955us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.590s	61.521us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.090s	393.946us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.560s	11.839us	0	1	0.00
		sram_ctrl_tl_intg_err	2.090s	125.138us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.560s	11.839us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.090s	125.138us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.131m	24.239ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.131m	24.239ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.630s	35.501us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.727m	17.811ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.727m	17.811ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.727m	17.811ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.470s	601.503us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.700s	147.136us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.090s	393.946us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.710s	33.491us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	6.770s	207.699us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	6.770s	207.699us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.727m	17.811ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.560s	11.839us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.470s	601.503us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.560s	11.839us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.560s	11.839us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	6.770s	207.699us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.560s	11.839us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.141m	2.631ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.37118010240787288112715968733373992319024967919820544904941043230786465045033
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  11839492 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  11839492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---