SYSRST_CTRL Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 2.560s 2.129ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 2.640s 2.479ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 2.730s 2.448ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.910s 2.319ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 3.520s 4.052ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 6.130s 2.054ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 8.780s 14.176ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 10.160s 3.167ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 3.470s 2.161ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 6.130s 2.054ms 1 1 100.00
sysrst_ctrl_csr_aliasing 10.160s 3.167ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.603m 60.930ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 2.367m 77.876ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 7.770s 3.547ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 2.730s 3.486ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 2.770s 2.539ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 3.800s 2.151ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 6.220s 2.414ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 7.180s 2.608ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 3.570s 9.009ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.096m 33.542ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 6.840s 7.609ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 5.260s 2.016ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 3.370s 2.024ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 6.880s 2.078ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 6.880s 2.078ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 3.520s 4.052ms 1 1 100.00
sysrst_ctrl_csr_rw 6.130s 2.054ms 1 1 100.00
sysrst_ctrl_csr_aliasing 10.160s 3.167ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.480s 5.070ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 3.520s 4.052ms 1 1 100.00
sysrst_ctrl_csr_rw 6.130s 2.054ms 1 1 100.00
sysrst_ctrl_csr_aliasing 10.160s 3.167ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.480s 5.070ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 13.590s 22.062ms 1 1 100.00
sysrst_ctrl_tl_intg_err 25.280s 22.220ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 25.280s 22.220ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 3.350s 9.700ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00