UART Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.100s	266.101us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.650s	81.071us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.750s	30.896us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.980s	35.539us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.580s	29.113us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.560s	67.984us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.750s	30.896us	1	1	100.00
		uart_csr_aliasing	1.580s	29.113us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	37.020s	91.743ms	1	1	100.00
V2	parity	uart_smoke	2.100s	266.101us	1	1	100.00
		uart_tx_rx	37.020s	91.743ms	1	1	100.00
V2	parity_error	uart_intr	5.020s	7.039ms	1	1	100.00
		uart_rx_parity_err	28.000s	45.719ms	1	1	100.00
V2	watermark	uart_tx_rx	37.020s	91.743ms	1	1	100.00
		uart_intr	5.020s	7.039ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.129m	124.966ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.676m	81.435ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	38.010s	222.132ms	1	1	100.00
V2	rx_frame_err	uart_intr	5.020s	7.039ms	1	1	100.00
V2	rx_break_err	uart_intr	5.020s	7.039ms	1	1	100.00
V2	rx_timeout	uart_intr	5.020s	7.039ms	1	1	100.00
V2	perf	uart_perf	3.825m	23.042ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.950s	6.148ms	1	1	100.00
V2	line_loopback	uart_loopback	5.950s	6.148ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	7.170s	5.101ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	17.390s	43.217ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.780s	778.910us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	8.980s	1.901ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	5.884m	94.204ms	1	1	100.00
V2	stress_all	uart_stress_all	31.733m	461.599ms	1	1	100.00
V2	alert_test	uart_alert_test	1.640s	93.138us	1	1	100.00
V2	intr_test	uart_intr_test	1.610s	42.940us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.360s	36.268us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.360s	36.268us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.650s	81.071us	1	1	100.00
		uart_csr_rw	1.750s	30.896us	1	1	100.00
		uart_csr_aliasing	1.580s	29.113us	1	1	100.00
		uart_same_csr_outstanding	1.820s	43.849us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.650s	81.071us	1	1	100.00
		uart_csr_rw	1.750s	30.896us	1	1	100.00
		uart_csr_aliasing	1.580s	29.113us	1	1	100.00
		uart_same_csr_outstanding	1.820s	43.849us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.740s	196.288us	1	1	100.00
		uart_tl_intg_err	1.810s	109.005us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.810s	109.005us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.412m	3.795ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.113609435573267621865366647072126821706126098610530406717851953114336084032265
      Line 71, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 4329209125 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 4333271755 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 4342678306 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 4350376469 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 4356564167 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0