CHIP Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: `952e1dd`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.342m	3.050ms	1	1	100.00
		chip_sw_example_rom	55.710s	2.285ms	1	1	100.00
		chip_sw_example_manufacturer	2.270m	2.708ms	1	1	100.00
		chip_sw_example_concurrency	1.804m	2.069ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.510m	5.250ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.372m	4.097ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	5.910m	6.747ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.156h	34.747ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	45.310s	2.396ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.156h	34.747ms	1	1	100.00
		chip_csr_rw	3.372m	4.097ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.560s	48.379us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.237m	4.155ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.237m	4.155ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.237m	4.155ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.080m	4.128ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.080m	4.128ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.229m	4.591ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.363m	4.739ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	4.833m	3.986ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	4.039m	3.227ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	6.789m	4.025ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.934m	4.084ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.883m	5.447ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.883m	5.447ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.246m	3.251ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.779m	3.334ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.984m	3.907ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	2.794m	3.504ms	1	1	100.00
		chip_tap_straps_testunlock0	3.410m	4.201ms	1	1	100.00
		chip_tap_straps_rma	3.343m	4.573ms	1	1	100.00
		chip_tap_straps_prod	1.673m	3.443ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.627m	3.018ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.844m	9.462ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.844m	5.642ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.844m	5.642ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.192m	7.595ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	26.739m	18.633ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.650m	4.241ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.948m	5.494ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.545m	17.576ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.876m	2.558ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.856m	6.521ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.054m	3.114ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	22.954m	13.247ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.665m	2.740ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.933m	4.683ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.442m	2.313ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.707m	3.214ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.997m	8.617ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.540m	5.680ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.933m	3.329ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.540m	5.680ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.396m	3.087ms	1	1	100.00
		chip_sw_aes_smoketest	2.717m	3.437ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.405m	2.976ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.352m	2.910ms	1	1	100.00
		chip_sw_csrng_smoketest	2.758m	3.108ms	1	1	100.00
		chip_sw_entropy_src_smoketest	5.238m	3.973ms	1	1	100.00
		chip_sw_gpio_smoketest	2.100m	3.433ms	1	1	100.00
		chip_sw_hmac_smoketest	2.733m	3.309ms	1	1	100.00
		chip_sw_kmac_smoketest	2.258m	3.001ms	1	1	100.00
		chip_sw_otbn_smoketest	9.225m	5.257ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.543m	6.337ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.005m	5.841ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.263m	3.421ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.513m	2.761ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.031m	3.122ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.293m	2.986ms	1	1	100.00
		chip_sw_uart_smoketest	2.524m	2.431ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.760m	3.436ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.429m	4.262ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.926h	61.183ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.056m	14.935ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.381m	5.784ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.445m	2.924ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.744m	3.394ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.858h	52.901ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.801h	57.398ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	43.730s	2.677ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	43.730s	2.677ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.156h	34.747ms	1	1	100.00
		chip_same_csr_outstanding	18.351m	15.876ms	1	1	100.00
		chip_csr_hw_reset	2.510m	5.250ms	1	1	100.00
		chip_csr_rw	3.372m	4.097ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.156h	34.747ms	1	1	100.00
		chip_same_csr_outstanding	18.351m	15.876ms	1	1	100.00
		chip_csr_hw_reset	2.510m	5.250ms	1	1	100.00
		chip_csr_rw	3.372m	4.097ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	27.820s	542.621us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.690s	56.323us	1	1	100.00
		xbar_smoke_large_delays	56.070s	8.729ms	1	1	100.00
		xbar_smoke_slow_rsp	55.450s	6.407ms	1	1	100.00
		xbar_random_zero_delays	22.230s	415.564us	1	1	100.00
		xbar_random_large_delays	3.087m	31.053ms	1	1	100.00
		xbar_random_slow_rsp	27.490s	3.082ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	5.320s	35.332us	1	1	100.00
		xbar_error_and_unmapped_addr	13.300s	147.643us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	44.040s	2.416ms	1	1	100.00
		xbar_error_and_unmapped_addr	13.300s	147.643us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	41.960s	1.901ms	1	1	100.00
		xbar_access_same_device_slow_rsp	3.239m	22.447ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	15.040s	722.953us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	15.540s	553.154us	1	1	100.00
		xbar_stress_all_with_error	2.704m	3.842ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.042m	330.527us	1	1	100.00
		xbar_stress_all_with_reset_error	30.460s	141.882us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.056m	14.935ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.906m	29.719ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	39.215m	14.731ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.599m	10.626ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	41.454m	15.456ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	38.857m	15.615ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.798m	15.131ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.780m	14.305ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	17.600s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.050s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	18.780s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	19.260s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.860s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	18.950s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	19.620s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.950s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.970s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.910s	10.260us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	15.390s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.170s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	15.530s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	15.600s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	15.950s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.370s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	15.820s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	15.950s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.340s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	15.710s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.000s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.780s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	15.770s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.220s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.350s	10.260us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.755m	10.743ms	1	1	100.00
		rom_e2e_asm_init_dev	38.778m	15.297ms	1	1	100.00
		rom_e2e_asm_init_prod	38.009m	15.892ms	1	1	100.00
		rom_e2e_asm_init_prod_end	38.678m	15.915ms	1	1	100.00
		rom_e2e_asm_init_rma	35.479m	15.009ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.273m	15.236ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	36.963m	15.305ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	34.656m	15.205ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.753m	16.323ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.245m	35.121ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.245m	35.121ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.092m	2.538ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.876m	2.558ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.633m	3.250ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.797m	3.540ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	23.948m	13.097ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.047m	3.170ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	6.005m	5.126ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.935m	5.725ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	7.806m	5.139ms	1	1	100.00
		chip_plic_all_irqs_10	3.861m	4.078ms	1	1	100.00
		chip_plic_all_irqs_20	5.493m	4.096ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.457m	3.556ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.128m	14.099ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.004m	4.250ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.710m	2.498ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.667m	12.047ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.278m	8.104ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.956m	8.029ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.321m	7.427ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.860h	255.698ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.560m	4.357ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.543m	6.337ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.560m	4.357ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.041m	8.215ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.041m	8.215ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.201m	7.047ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.111m	6.071ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.663m	5.745ms	1	1	100.00
		chip_sw_aes_idle	2.797m	3.540ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.019m	2.939ms	1	1	100.00
		chip_sw_kmac_idle	1.910m	2.235ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.418m	3.874ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.107m	4.341ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.202m	4.190ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.282m	4.235ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.583m	11.385ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.165m	4.834ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.195m	4.453ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	4.988m	3.591ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.006m	4.155ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.677m	3.479ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.309m	4.648ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.192m	7.595ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	8.387m	8.425ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	4.988m	3.591ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.006m	4.155ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.650m	4.241ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.948m	5.494ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.545m	17.576ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.876m	2.558ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.856m	6.521ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.054m	3.114ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	22.954m	13.247ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.665m	2.740ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.933m	4.683ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.442m	2.313ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.460m	2.545ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.185m	4.461ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.891m	6.964ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	48.683m	24.061ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.486m	3.335ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.128m	2.660ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.894m	6.952ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.980m	3.267ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.252m	5.415ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	17.745m	18.411ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	27.762m	17.548ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.192m	7.595ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	4.503m	4.011ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.063m	3.178ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.935m	5.725ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	16.278m	8.104ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.798m	7.437ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.767m	3.654ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.646m	5.925ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.275m	2.594ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	56.971m	22.743ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.909m	2.485ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.631m	6.295ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.909m	2.485ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.798m	7.437ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.193m	2.939ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	19.992m	19.330ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	7.904m	5.546ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.948m	5.494ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.364m	3.815ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	4.650m	4.241ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	57.803m	42.608ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	19.992m	19.330ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.810m	3.832ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	12.625m	7.503ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.213m	5.477ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	57.803m	42.608ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.213m	5.477ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.213m	5.477ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.213m	5.477ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.213m	5.477ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.935m	5.725ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.925m	4.254ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.885m	4.684ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.099m	5.696ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.099m	5.696ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.616m	3.192ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.054m	3.114ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.019m	2.939ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.493m	2.497ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	4.832m	3.365ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.509m	4.635ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.185m	4.376ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.093m	5.968ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.807m	3.612ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	12.625m	7.503ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	22.954m	13.247ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	19.484m	9.874ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	23.948m	13.097ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	36.564m	12.259ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.857m	2.265ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.756m	3.577ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.665m	2.740ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	12.625m	7.503ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.814m	7.758ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.556m	3.314ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	9.328m	5.680ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.910m	2.235ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	6.005m	5.126ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	2.794m	3.504ms	1	1	100.00
		chip_tap_straps_rma	3.343m	4.573ms	1	1	100.00
		chip_tap_straps_prod	1.673m	3.443ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.401m	2.928ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.814m	7.758ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.814m	7.758ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.814m	7.758ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.744m	6.756ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.213m	5.477ms	1	1	100.00
		chip_sw_flash_rma_unlocked	57.803m	42.608ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.206m	2.730ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.728m	6.541ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.402m	5.726ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.098m	7.598ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.814m	7.758ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.625m	7.503ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.176m	9.155ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.963m	7.869ms	1	1	100.00
		chip_prim_tl_access	1.925m	4.254ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	8.387m	8.425ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.165m	4.834ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.195m	4.453ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	4.988m	3.591ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.006m	4.155ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.677m	3.479ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.309m	4.648ms	1	1	100.00
		chip_tap_straps_dev	2.794m	3.504ms	1	1	100.00
		chip_tap_straps_rma	3.343m	4.573ms	1	1	100.00
		chip_tap_straps_prod	1.673m	3.443ms	1	1	100.00
		chip_rv_dm_lc_disabled	7.848m	24.374ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	1.653m	3.782ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.564m	3.505ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.374m	2.883ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.305m	4.044ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	24.492m	34.308ms	1	1	100.00
		chip_rv_dm_lc_disabled	7.848m	24.374ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.033h	46.373ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.052h	47.040ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.368m	7.156ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.012h	46.243ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	24.492m	34.308ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.167m	2.304ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.013m	2.412ms	1	1	100.00
		rom_volatile_raw_unlock	59.530s	2.931ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.312m	15.989ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.545m	17.576ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.663m	5.745ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.663m	5.745ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.663m	5.745ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	3.674m	3.693ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.814m	7.758ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	19.992m	19.330ms	1	1	100.00
		chip_sw_otbn_mem_scramble	3.674m	3.693ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.625m	7.503ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.439m	5.251ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.325m	3.010ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	19.992m	19.330ms	1	1	100.00
		chip_sw_otbn_mem_scramble	3.674m	3.693ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.625m	7.503ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.439m	5.251ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.325m	3.010ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.814m	7.758ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.476m	5.157ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.401m	2.928ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.206m	2.730ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.728m	6.541ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.402m	5.726ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.098m	7.598ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.814m	7.758ms	1	1	100.00
		chip_prim_tl_access	1.925m	4.254ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.925m	4.254ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.789m	8.851ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.007m	7.437ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	19.288m	27.312ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.681m	7.503ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.878m	8.155ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.172m	6.502ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.386m	19.722ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	15.229m	13.209ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.041m	8.215ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.155m	9.620ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.982m	3.737ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.007m	7.437ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	2.923m	4.660ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	28.268m	34.316ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.528m	6.878ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.194m	6.812ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.198m	17.710ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.731m	8.064ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	15.400m	12.499ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	20.127m	20.052ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.228m	2.447ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.935m	5.725ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.176m	9.155ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.176m	9.155ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	15.400m	12.499ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.198m	17.710ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.982m	3.737ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.543m	6.337ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.375m	4.625ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	2.796m	4.240ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.810m	4.942ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.128m	14.099ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.305m	2.694ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.935m	5.725ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.956m	8.029ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.032m	4.644ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.461m	4.525ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.647m	3.063ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.325m	3.010ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	2.796m	4.240ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	2.796m	4.240ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	15.517m	14.764ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.596m	13.178ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.375m	4.625ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.662m	4.294ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.051m	5.872ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.343m	4.573ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	7.848m	24.374ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	7.806m	5.139ms	1	1	100.00
		chip_plic_all_irqs_10	3.861m	4.078ms	1	1	100.00
		chip_plic_all_irqs_20	5.493m	4.096ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.792m	2.668ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.469m	2.443ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.056m	14.935ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.244m	8.285ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.366m	3.055ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.720m	2.756ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.595m	3.085ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.439m	5.251ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.933m	4.683ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.094m	6.163ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.319m	9.321ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.963m	7.869ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.935m	5.725ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.844m	5.642ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.731m	8.064ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.954m	23.222ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.561m	2.770ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.910m	3.562ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.617m	4.463ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.954m	23.222ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.954m	23.222ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	12.132m	11.636ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	12.132m	11.636ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.464m	5.985ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.245m	35.121ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.588m	3.195ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.853m	3.093ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.581m	3.599ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.833m	3.673ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.489m	7.434ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.248h	30.829ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	28.430m	11.937ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.317m	3.345ms	1	1	100.00
V2		TOTAL			238	275	86.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.885m	3.351ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.419m	2.633ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.362h	72.218ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.782m	5.382ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.098m	10.243ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.092m	11.264ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.735m	10.059ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.183m	4.487ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.335m	3.795ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.256m	4.905ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.739s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.609m	5.185ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.693m	3.272ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	15.226m	6.154ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	19.486m	9.615ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.249m	2.441ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	7.966m	5.264ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.101m	2.257ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.220m	4.984ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.771m	6.811ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.346m	5.509ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	15.400m	12.499ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.098m	10.243ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.092m	11.264ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.735m	10.059ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.055m	6.042ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.935m	5.725ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.390h	38.118ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.390h	38.118ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.467m	2.830ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.080m	4.128ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	48.282m	18.756ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.214m	2.668ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.520m	5.745ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.560m	3.345ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.651m	3.804ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.323m	3.941ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.249s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.072m	2.892ms	1	1	100.00
		TOTAL			285	325	87.69

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.85312640318862869287730185984439554691317875282971593478321729844909188754894
    Line 611, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.26657140032064924407744479577266200927813243850033815377379951161856820946570
    Line 674, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.83145156830600411976962890414192414733523749811875067401459353938914124421344
    Line 652, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.104428251278656554751793319215110769015820292368326473805633305914793095288678
    Line 655, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.794467393247939167673698005896372477657938326348240361394023841488462053075
    Line 690, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.24751370259466087131989742742711572102534382115632077055592269070573143152503
    Line 582, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.102407877040251105672626585266452131040162023455387475583199895369530078364967
    Line 579, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.17798608562965394113440427694956576866213514004478380047770210957411275163104
    Line 575, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1936208953108049514063471728353649598146944343858655220120261995143217530043
    Line 592, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.44047899054233639964168790783877870869259990367136219594028482974684070529076
    Line 609, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.45319049909449179615588103302276580424062887058065759189504705027136293240519
    Line 793, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.34513893707033876620207553368250885328240480003924011241695481435430019394301
    Line 694, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.28686601290718530666793792052548026072835761925097946242154208535073341944426
    Line 721, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.14543269269114359419753136294288255148235744684198662128520043988913526187615
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.156s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.25772991556023363856528003370645990513546135358308274580867720164455756088758
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.145s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.85300673112307847791581766259881039721468181209095775667224972720069988144105
    Line 815, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.21651416455914158771861193059682746637009756812164083477909767421086547112120
    Line 743, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.35793779327001700634519677116091213498475057355561760152641471096765029219632
    Line 730, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4669017420836081863952200354668620076111303863975814484503897128051458346105
    Line 712, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.76072791543511299968228062420713327116184703624702612330927018229373431429213
    Line 646, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3251.022000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3251.022000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.97026993204725926426788909941334644104005059125072506107924730042796273663268
    Line 431, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3054.590160 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3054.590160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@80115) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.24771353158210766205631651056734714298103884563871614116503053821451036412585
Line 450, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4240.190148 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@80115) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4240.190148 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.36515282559848379724450293597582691280156575743417976219356670911904420114413
    Line 435, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11635.516748 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11635.516748 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.23704980746792456177264322062297881359932366122537741373375200083048296319352
    Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 35120.697974 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 35120.697974 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.113446193391180173816343526743191938322603680529326015916458353315610933047231
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3169.684760 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3169.684760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.27748680467685177238171784461527675951156835203686801984560550892513075522771
    Line 420, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2497.994600 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2497.994600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.69743012681232871086456807753165982412100162866805637411353062497189179382320
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 3654.297096 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 3654.297096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31915) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.94316487485063913484180232811576668962206319850947072398965852609450481249334
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2676.900278 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31915) { a_addr: 'h10374  a_data: 'he1bf1c9b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h17  a_opcode: 'h4  a_user: 'h192bf  d_param: 'h0  d_source: 'h17  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2676.900278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.101907602398397590510868544467645934329807573706220153485220644565446645480789
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2923.782000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2923.782000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.85595226788908628838317688094299996186410317783577490395531346399461374447330
    Line 424, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3393.851000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3393.851000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.49429313318707504367270786462392365099326878353047424897297571040015199054600
    Line 436, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 18632.509769 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 18632.509769 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.110763377802661104240110054563346156111036253047678706370348100085356615713355
    Line 663, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.32667430008059830901253233059863818408378846983639536747036520769675311270218
    Line 621, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31801) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.34681853899048364728683818540624189792459797508585511389646442115719787220306
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2395.763740 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31801) { a_addr: 'h10544  a_data: 'h8b720ee8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h28  a_opcode: 'h4  a_user: 'h1b6ad  d_param: 'h0  d_source: 'h28  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2395.763740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---