ADC_CTRL Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	6.480s	5.665ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.430s	1.314ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.870s	344.571us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	8.860s	18.271ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.900s	890.615us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.410s	480.741us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.870s	344.571us	1	1	100.00
		adc_ctrl_csr_aliasing	3.900s	890.615us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	3.658m	493.865ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	4.567m	164.474ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	2.409m	163.963ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	4.260m	158.694ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	17.075m	605.532ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.427m	195.074ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	2.577m	334.666ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.810s	2.269ms	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.880s	3.583ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	37.580s	45.608ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	20.100s	116.909ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	7.090m	528.402ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.690s	285.471us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.860s	349.265us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.730s	677.862us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.730s	677.862us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.430s	1.314ms	1	1	100.00
		adc_ctrl_csr_rw	1.870s	344.571us	1	1	100.00
		adc_ctrl_csr_aliasing	3.900s	890.615us	1	1	100.00
		adc_ctrl_same_csr_outstanding	9.950s	4.919ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.430s	1.314ms	1	1	100.00
		adc_ctrl_csr_rw	1.870s	344.571us	1	1	100.00
		adc_ctrl_csr_aliasing	3.900s	890.615us	1	1	100.00
		adc_ctrl_same_csr_outstanding	9.950s	4.919ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	4.940s	4.439ms	1	1	100.00
		adc_ctrl_tl_intg_err	3.830s	5.029ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	3.830s	5.029ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.610s	4.537ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.601885785760729002630550073368523275265320005471107895194202201865475230477
      Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 2269119755 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 2269119755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---