EDN Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.730s	60.459us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.770s	26.966us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.710s	15.108us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.700s	265.170us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.110s	118.265us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.820s	38.449us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.710s	15.108us	1	1	100.00
		edn_csr_aliasing	2.110s	118.265us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	3.880s	260.239us	1	1	100.00
V2	csrng_commands	edn_genbits	3.880s	260.239us	1	1	100.00
V2	genbits	edn_genbits	3.880s	260.239us	1	1	100.00
V2	interrupts	edn_intr	1.760s	25.472us	1	1	100.00
V2	alerts	edn_alert	1.980s	27.731us	1	1	100.00
V2	errs	edn_err	1.790s	60.497us	1	1	100.00
V2	disable	edn_disable	1.780s	21.145us	1	1	100.00
		edn_disable_auto_req_mode	1.900s	33.493us	1	1	100.00
V2	stress_all	edn_stress_all	3.960s	276.486us	1	1	100.00
V2	intr_test	edn_intr_test	1.630s	22.222us	1	1	100.00
V2	alert_test	edn_alert_test	1.720s	21.958us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.680s	71.171us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.680s	71.171us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.770s	26.966us	1	1	100.00
		edn_csr_rw	1.710s	15.108us	1	1	100.00
		edn_csr_aliasing	2.110s	118.265us	1	1	100.00
		edn_same_csr_outstanding	2.080s	129.555us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.770s	26.966us	1	1	100.00
		edn_csr_rw	1.710s	15.108us	1	1	100.00
		edn_csr_aliasing	2.110s	118.265us	1	1	100.00
		edn_same_csr_outstanding	2.080s	129.555us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.640s	1.181ms	1	1	100.00
		edn_tl_intg_err	2.590s	298.076us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.890s	17.665us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.980s	27.731us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.640s	1.181ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.640s	1.181ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.640s	1.181ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.640s	1.181ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.980s	27.731us	1	1	100.00
		edn_sec_cm	4.640s	1.181ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.980s	27.731us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.590s	298.076us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	56.530s	7.394ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00