HMAC Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.930s 434.293us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.580s 103.678us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.580s 26.007us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.530s 1.877ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.080s 1.137ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.640s 19.077us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.580s 26.007us 1 1 100.00
hmac_csr_aliasing 6.080s 1.137ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 1.193m 1.785ms 1 1 100.00
V2 back_pressure hmac_back_pressure 29.880s 777.948us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.370s 3.068ms 1 1 100.00
hmac_test_sha384_vectors 20.410s 525.094us 1 1 100.00
hmac_test_sha512_vectors 7.262m 14.088ms 1 1 100.00
hmac_test_hmac256_vectors 7.170s 194.751us 1 1 100.00
hmac_test_hmac384_vectors 9.320s 1.223ms 1 1 100.00
hmac_test_hmac512_vectors 8.080s 740.905us 1 1 100.00
V2 burst_wr hmac_burst_wr 18.890s 1.032ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 11.554m 39.987ms 1 1 100.00
V2 error hmac_error 19.910s 2.035ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 22.880s 2.630ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.930s 434.293us 1 1 100.00
hmac_long_msg 1.193m 1.785ms 1 1 100.00
hmac_back_pressure 29.880s 777.948us 1 1 100.00
hmac_datapath_stress 11.554m 39.987ms 1 1 100.00
hmac_burst_wr 18.890s 1.032ms 1 1 100.00
hmac_stress_all 56.530s 6.662ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.930s 434.293us 1 1 100.00
hmac_long_msg 1.193m 1.785ms 1 1 100.00
hmac_back_pressure 29.880s 777.948us 1 1 100.00
hmac_datapath_stress 11.554m 39.987ms 1 1 100.00
hmac_wipe_secret 22.880s 2.630ms 1 1 100.00
hmac_test_sha256_vectors 8.370s 3.068ms 1 1 100.00
hmac_test_sha384_vectors 20.410s 525.094us 1 1 100.00
hmac_test_sha512_vectors 7.262m 14.088ms 1 1 100.00
hmac_test_hmac256_vectors 7.170s 194.751us 1 1 100.00
hmac_test_hmac384_vectors 9.320s 1.223ms 1 1 100.00
hmac_test_hmac512_vectors 8.080s 740.905us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.930s 434.293us 1 1 100.00
hmac_long_msg 1.193m 1.785ms 1 1 100.00
hmac_back_pressure 29.880s 777.948us 1 1 100.00
hmac_datapath_stress 11.554m 39.987ms 1 1 100.00
hmac_burst_wr 18.890s 1.032ms 1 1 100.00
hmac_error 19.910s 2.035ms 1 1 100.00
hmac_wipe_secret 22.880s 2.630ms 1 1 100.00
hmac_test_sha256_vectors 8.370s 3.068ms 1 1 100.00
hmac_test_sha384_vectors 20.410s 525.094us 1 1 100.00
hmac_test_sha512_vectors 7.262m 14.088ms 1 1 100.00
hmac_test_hmac256_vectors 7.170s 194.751us 1 1 100.00
hmac_test_hmac384_vectors 9.320s 1.223ms 1 1 100.00
hmac_test_hmac512_vectors 8.080s 740.905us 1 1 100.00
hmac_stress_all 56.530s 6.662ms 1 1 100.00
V2 stress_all hmac_stress_all 56.530s 6.662ms 1 1 100.00
V2 alert_test hmac_alert_test 1.390s 16.205us 1 1 100.00
V2 intr_test hmac_intr_test 1.640s 23.124us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.830s 607.539us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.830s 607.539us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.580s 103.678us 1 1 100.00
hmac_csr_rw 1.580s 26.007us 1 1 100.00
hmac_csr_aliasing 6.080s 1.137ms 1 1 100.00
hmac_same_csr_outstanding 1.900s 77.203us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.580s 103.678us 1 1 100.00
hmac_csr_rw 1.580s 26.007us 1 1 100.00
hmac_csr_aliasing 6.080s 1.137ms 1 1 100.00
hmac_same_csr_outstanding 1.900s 77.203us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.730s 104.849us 1 1 100.00
hmac_tl_intg_err 3.770s 532.839us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.770s 532.839us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.930s 434.293us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.660s 39.244us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 21.010s 6.870ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.030s 79.920us 1 1 100.00
TOTAL 28 28 100.00