I2C Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	18.340s	3.399ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	18.580s	1.072ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.770s	30.270us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.560s	20.787us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.060s	743.904us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.970s	198.356us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.260s	30.099us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.560s	20.787us	1	1	100.00
		i2c_csr_aliasing	1.970s	198.356us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.060s	110.440us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	14.524m	32.764ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	4.890s	482.134us	1	1	100.00
V2	host_override	i2c_host_override	1.440s	46.301us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.497m	20.633ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	50.460s	2.502ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.810s	460.786us	1	1	100.00
		i2c_host_fifo_fmt_empty	6.320s	410.747us	1	1	100.00
		i2c_host_fifo_reset_rx	4.520s	226.543us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.236m	1.984ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.390s	1.283ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.520s	109.010us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.170s	2.374ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	19.660s	14.324ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.130s	590.257us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	5.360s	4.538ms	1	1	100.00
		i2c_target_intr_smoke	4.090s	1.289ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.840s	120.951us	1	1	100.00
		i2c_target_fifo_reset_tx	1.900s	600.388us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	9.360s	22.168ms	1	1	100.00
		i2c_target_stress_rd	5.360s	4.538ms	1	1	100.00
		i2c_target_intr_stress_wr	1.677m	15.965ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.060s	1.065ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	29.740s	3.845ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.420s	1.037ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.340s	876.403us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.550s	395.657us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.980s	756.096us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	4.890s	482.134us	1	1	100.00
		i2c_host_perf_precise	2.220s	181.939us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.390s	1.283ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.160s	182.341us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.190s	592.337us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.910s	2.041ms	1	1	100.00
		i2c_target_nack_txstretch	2.120s	607.831us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	10.430s	351.276us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.660s	913.752us	1	1	100.00
V2	alert_test	i2c_alert_test	1.780s	24.637us	1	1	100.00
V2	intr_test	i2c_intr_test	1.410s	61.655us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.940s	38.921us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.940s	38.921us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.770s	30.270us	1	1	100.00
		i2c_csr_rw	1.560s	20.787us	1	1	100.00
		i2c_csr_aliasing	1.970s	198.356us	1	1	100.00
		i2c_same_csr_outstanding	1.820s	223.118us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.770s	30.270us	1	1	100.00
		i2c_csr_rw	1.560s	20.787us	1	1	100.00
		i2c_csr_aliasing	1.970s	198.356us	1	1	100.00
		i2c_same_csr_outstanding	1.820s	223.118us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.440s	269.352us	1	1	100.00
		i2c_sec_cm	1.770s	161.912us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.440s	269.352us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	3.130s	215.889us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.990s	147.291us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	9.870s	3.081ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.14677014217942504446328619053539730706536127458650502295269061553551980275359
      Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 215888874 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 215888874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.60853355529994970057353446830685471118021377622194795632907935273745661195826
      Line 107, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3081077554 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3081077554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.113751703175261504065225037542067645957625460282840780747593049753055020126456
      Line 217, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 32763519631 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @9442634
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.86369941143394384722033350866911226754692282586433652539130662523893938239030
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 147291482 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 147291482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.115498323971951952270542770884753910528931838481614098133740080331103414021899
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_FATAL @ 109010269 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x8d3b2914, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 109010269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.47137738722858794898711634674747415214354046012923873358955481506660561785282
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 607830896 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 607830896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---