KEYMGR Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	4.240s	218.676us	1	1	100.00
V1	random	keymgr_random	2.990s	45.016us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.860s	41.565us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.780s	45.060us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	6.220s	137.768us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	6.910s	572.311us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.840s	126.144us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.780s	45.060us	1	1	100.00
		keymgr_csr_aliasing	6.910s	572.311us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	5.540s	228.613us	1	1	100.00
V2	sideload	keymgr_sideload	3.450s	63.433us	1	1	100.00
		keymgr_sideload_kmac	6.640s	751.151us	1	1	100.00
		keymgr_sideload_aes	3.310s	66.528us	1	1	100.00
		keymgr_sideload_otbn	2.970s	65.451us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	5.180s	271.585us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.400s	97.950us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.900s	225.693us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	25.320s	2.771ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	5.230s	259.675us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.940s	236.004us	1	1	100.00
V2	stress_all	keymgr_stress_all	25.440s	923.949us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.870s	10.384us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.910s	15.042us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.480s	494.698us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.480s	494.698us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.860s	41.565us	1	1	100.00
		keymgr_csr_rw	1.780s	45.060us	1	1	100.00
		keymgr_csr_aliasing	6.910s	572.311us	1	1	100.00
		keymgr_same_csr_outstanding	2.430s	46.436us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.860s	41.565us	1	1	100.00
		keymgr_csr_rw	1.780s	45.060us	1	1	100.00
		keymgr_csr_aliasing	6.910s	572.311us	1	1	100.00
		keymgr_same_csr_outstanding	2.430s	46.436us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	10.000s	858.355us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	10.000s	858.355us	1	1	100.00
		keymgr_tl_intg_err	2.690s	134.752us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.350s	163.696us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.350s	163.696us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.350s	163.696us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.350s	163.696us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	7.130s	2.289ms	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	10.000s	858.355us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	10.000s	858.355us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.690s	134.752us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.350s	163.696us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	5.540s	228.613us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.990s	45.016us	1	1	100.00
		keymgr_csr_rw	1.780s	45.060us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.990s	45.016us	1	1	100.00
		keymgr_csr_rw	1.780s	45.060us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.990s	45.016us	1	1	100.00
		keymgr_csr_rw	1.780s	45.060us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.400s	97.950us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	5.230s	259.675us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	5.230s	259.675us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.990s	45.016us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	5.380s	180.323us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	10.000s	858.355us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	10.000s	858.355us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	10.000s	858.355us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.460s	333.974us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.400s	97.950us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	10.000s	858.355us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	10.000s	858.355us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	10.000s	858.355us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.460s	333.974us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.460s	333.974us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	10.000s	858.355us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.460s	333.974us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	10.000s	858.355us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.460s	333.974us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	6.620s	505.364us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.83237239147220448793061178387892861848184113342217869154811920778628441006349
      Line 100, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
        UVM_ERROR @ 134752075 ps: (keymgr_csr_assert_fpv.sv:442) [ASSERT FAILED] sealing_sw_binding_7_rd_A
        UVM_INFO @ 134752075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---