KMAC/MASKED Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	41.490s	18.894ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.110s	18.919us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.870s	58.675us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.320s	220.769us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.560s	146.758us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.830s	320.292us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.870s	58.675us	1	1	100.00
		kmac_csr_aliasing	6.560s	146.758us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.670s	15.510us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.180s	95.176us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	55.626m	97.662ms	1	1	100.00
V2	burst_write	kmac_burst_write	53.430s	1.403ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.430m	1.239s	1	1	100.00
		kmac_test_vectors_sha3_256	31.601m	367.542ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.624m	160.479ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.648m	39.053ms	1	1	100.00
		kmac_test_vectors_shake_128	1.932m	6.963ms	1	1	100.00
		kmac_test_vectors_shake_256	29.825m	361.327ms	1	1	100.00
		kmac_test_vectors_kmac	3.180s	266.659us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.180s	82.563us	1	1	100.00
V2	sideload	kmac_sideload	3.792m	4.818ms	1	1	100.00
V2	app	kmac_app	1.017m	7.285ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.917m	4.615ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.011m	14.649ms	1	1	100.00
V2	error	kmac_error	3.155m	8.380ms	1	1	100.00
V2	key_error	kmac_key_error	5.300s	1.306ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	5.160s	156.565us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	35.110s	1.993ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.890s	127.826us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	4.480s	700.971us	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	3.110s	57.005us	1	1	100.00
V2	stress_all	kmac_stress_all	6.938m	16.605ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.680s	41.845us	1	1	100.00
V2	alert_test	kmac_alert_test	2.170s	73.463us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.740s	645.459us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.740s	645.459us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.110s	18.919us	1	1	100.00
		kmac_csr_rw	1.870s	58.675us	1	1	100.00
		kmac_csr_aliasing	6.560s	146.758us	1	1	100.00
		kmac_same_csr_outstanding	2.400s	66.610us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.110s	18.919us	1	1	100.00
		kmac_csr_rw	1.870s	58.675us	1	1	100.00
		kmac_csr_aliasing	6.560s	146.758us	1	1	100.00
		kmac_same_csr_outstanding	2.400s	66.610us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.680s	270.240us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.680s	270.240us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.680s	270.240us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.680s	270.240us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.410s	158.771us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	34.960s	11.528ms	1	1	100.00
		kmac_tl_intg_err	1.650s	8.491us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.650s	8.491us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	3.110s	57.005us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	41.490s	18.894ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.792m	4.818ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.680s	270.240us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	34.960s	11.528ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	34.960s	11.528ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	34.960s	11.528ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	41.490s	18.894ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	3.110s	57.005us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	34.960s	11.528ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	39.050s	1.618ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	41.490s	18.894ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	51.800s	1.864ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.77889240938352315862645038439790410746791511044698029670384715750909659778315
      Line 143, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1864231347 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1864231347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.43798171608953862408489666661500643338196359729168737718110085055920017924292
      Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
        UVM_ERROR @   8490917 ps: (kmac_csr_assert_fpv.sv:536) [ASSERT FAILED] prefix_6_rd_A
        UVM_INFO @   8490917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---