KMAC/UNMASKED Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	31.850s	950.821us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.800s	217.963us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.690s	32.127us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.180s	305.686us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.110s	1.447ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.730s	445.667us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.690s	32.127us	1	1	100.00
		kmac_csr_aliasing	6.110s	1.447ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.530s	72.239us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.710s	35.220us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	11.676m	40.264ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.978m	8.241ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.184m	60.366ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.040m	244.947ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.270s	2.300ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.060s	510.132us	1	1	100.00
		kmac_test_vectors_shake_128	2.567m	57.096ms	1	1	100.00
		kmac_test_vectors_shake_256	3.267m	8.140ms	1	1	100.00
		kmac_test_vectors_kmac	2.710s	107.640us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.640s	43.593us	1	1	100.00
V2	sideload	kmac_sideload	2.554m	6.046ms	1	1	100.00
V2	app	kmac_app	3.330m	20.035ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.034m	96.970ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.613m	10.753ms	1	1	100.00
V2	error	kmac_error	2.716m	6.622ms	1	1	100.00
V2	key_error	kmac_key_error	5.910s	1.509ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	15.230s	10.140ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	10.350s	2.762ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	11.610s	879.833us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	38.080s	6.938ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.790s	34.210us	1	1	100.00
V2	stress_all	kmac_stress_all	15.532m	231.023ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.590s	50.975us	1	1	100.00
V2	alert_test	kmac_alert_test	1.520s	28.549us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.350s	128.676us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.350s	128.676us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.800s	217.963us	1	1	100.00
		kmac_csr_rw	1.690s	32.127us	1	1	100.00
		kmac_csr_aliasing	6.110s	1.447ms	1	1	100.00
		kmac_same_csr_outstanding	2.000s	197.964us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.800s	217.963us	1	1	100.00
		kmac_csr_rw	1.690s	32.127us	1	1	100.00
		kmac_csr_aliasing	6.110s	1.447ms	1	1	100.00
		kmac_same_csr_outstanding	2.000s	197.964us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.000s	116.363us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.000s	116.363us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.000s	116.363us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.000s	116.363us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.220s	380.457us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	24.570s	14.667ms	1	1	100.00
		kmac_tl_intg_err	2.920s	804.131us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.920s	804.131us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.790s	34.210us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	31.850s	950.821us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.554m	6.046ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.000s	116.363us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	24.570s	14.667ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	24.570s	14.667ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	24.570s	14.667ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	31.850s	950.821us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.790s	34.210us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	24.570s	14.667ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.151m	4.032ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	31.850s	950.821us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.372m	4.981ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.49636141684195104202790921962110412276940189337461508240631614735696291647394
      Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10139652608 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa6fa6000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 10139652608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.29885821901346537078539559389650273934206410143603709519583254683624095115281
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
        UVM_ERROR @ 380456790 ps: (kmac_csr_assert_fpv.sv:554) [ASSERT FAILED] prefix_9_rd_A
        UVM_INFO @ 380456790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---