OTBN Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	250.819us	1	1	100.00
V1	single_binary	otbn_single	7.000s	105.449us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	22.111us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	37.336us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	193.816us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	30.286us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	6.000s	32.864us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	37.336us	1	1	100.00
		otbn_csr_aliasing	6.000s	30.286us	1	1	100.00
V1	mem_walk	otbn_mem_walk	16.000s	1.565ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	15.000s	712.047us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	23.000s	72.833us	1	1	100.00
V2	multi_error	otbn_multi_err	42.000s	207.195us	1	1	100.00
V2	back_to_back	otbn_multi	34.000s	2.570ms	1	1	100.00
V2	stress_all	otbn_stress_all	49.000s	192.515us	1	1	100.00
V2	lc_escalation	otbn_escalate	10.000s	168.568us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	21.949us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	8.000s	16.984us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	18.025us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	21.496us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	358.586us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	358.586us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	22.111us	1	1	100.00
		otbn_csr_rw	6.000s	37.336us	1	1	100.00
		otbn_csr_aliasing	6.000s	30.286us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	53.063us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	22.111us	1	1	100.00
		otbn_csr_rw	6.000s	37.336us	1	1	100.00
		otbn_csr_aliasing	6.000s	30.286us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	53.063us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	8.000s	44.402us	1	1	100.00
		otbn_dmem_err	8.000s	22.930us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	8.000s	346.468us	1	1	100.00
		otbn_controller_ispr_rdata_err	35.000s	164.415us	1	1	100.00
		otbn_mac_bignum_acc_err	11.000s	71.785us	1	1	100.00
		otbn_urnd_err	8.000s	13.489us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	59.427us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	22.004us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	46.377us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	9.000s	24.870us	0	1	0.00
		otbn_tl_intg_err	11.000s	70.014us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	22.000s	370.752us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	9.000s	24.870us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	9.000s	24.870us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	250.819us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	8.000s	22.930us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	8.000s	44.402us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	11.000s	70.014us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	10.000s	168.568us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	8.000s	44.402us	1	1	100.00
		otbn_dmem_err	8.000s	22.930us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	21.949us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	59.427us	1	1	100.00
		otbn_sec_cm	9.000s	24.870us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	9.000s	24.870us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	7.000s	105.449us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	8.000s	44.402us	1	1	100.00
		otbn_dmem_err	8.000s	22.930us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	21.949us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	59.427us	1	1	100.00
		otbn_sec_cm	9.000s	24.870us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	9.000s	24.870us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	10.000s	168.568us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	8.000s	44.402us	1	1	100.00
		otbn_dmem_err	8.000s	22.930us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	21.949us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	59.427us	1	1	100.00
		otbn_sec_cm	9.000s	24.870us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	9.000s	24.870us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	7.000s	105.449us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	73.241us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	31.847us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	24.000s	149.038us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	24.000s	149.038us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	8.000s	114.963us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	9.000s	24.870us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	9.000s	24.870us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	9.000s	234.673us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	9.000s	24.870us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	9.000s	24.870us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	22.938us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	22.938us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	7.000s	22.615us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	7.000s	105.449us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	7.000s	105.449us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	7.000s	105.449us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	34.000s	2.570ms	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	7.000s	105.449us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	7.000s	105.449us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	22.315us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	7.000s	105.449us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	9.000s	24.870us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.083m	1.802ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	41	95.12

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.60183367074169117880237537367945329254367785647591160399463952952235214037177
      Line 110, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 22615495 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  22615495 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  22615495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.104540154203137662756371890542429566983030766915924200950543228802005356758748
      Line 103, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 24870290 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 24870290 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  24870290 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  24870290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---