PATTGEN Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: `1215104`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	11.000s	166.924us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	57.039us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	10.918us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	119.360us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	27.144us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	16.335us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	10.918us	1	1	100.00
		pattgen_csr_aliasing	4.000s	27.144us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf			0	1	0.00
V2	cnt_rollover	cnt_rollover	41.000s	1.324ms	1	1	100.00
V2	error	pattgen_error	11.000s	84.527us	1	1	100.00
V2	stress_all	pattgen_stress_all	1.250m	11.235ms	0	1	0.00
V2	alert_test	pattgen_alert_test	7.000s	15.571us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	52.042us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	174.471us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	174.471us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	57.039us	1	1	100.00
		pattgen_csr_rw	4.000s	10.918us	1	1	100.00
		pattgen_csr_aliasing	4.000s	27.144us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	157.257us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	57.039us	1	1	100.00
		pattgen_csr_rw	4.000s	10.918us	1	1	100.00
		pattgen_csr_aliasing	4.000s	27.144us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	157.257us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	53.011us	1	1	100.00
		pattgen_sec_cm	9.000s	240.583us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	53.011us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	26.000s	1.914ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	9.000s	57.422us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

Job timed out after * minutes has 1 failures:
- Test pattgen_perf has 1 failures.
  - 0.pattgen_perf.43440387516558351154867025535226621503053673830310672115151615973242850495139
    Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.24381095436919603002137975879366861656446262670182881088614677277803062487568
Line 113, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 467535724 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 467543976 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 467543976 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 467643976 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.115427720477601667226546987999354915858989072663420900657823146356316094662467
    Line 149, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 11234523172 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10369
```