ROM_CTRL/32KB Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.140s 238.454us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.130s 136.527us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.940s 170.792us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.190s 370.908us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.120s 174.697us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.730s 648.826us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.940s 170.792us 1 1 100.00
rom_ctrl_csr_aliasing 5.120s 174.697us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.400s 724.627us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.490s 173.047us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.530s 405.222us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 13.580s 443.169us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.350s 741.851us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 3.700s 386.525us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.600s 536.849us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.600s 536.849us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.130s 136.527us 1 1 100.00
rom_ctrl_csr_rw 4.940s 170.792us 1 1 100.00
rom_ctrl_csr_aliasing 5.120s 174.697us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.230s 574.849us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.130s 136.527us 1 1 100.00
rom_ctrl_csr_rw 4.940s 170.792us 1 1 100.00
rom_ctrl_csr_aliasing 5.120s 174.697us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.230s 574.849us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 28.650s 2.155ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 14.640s 569.549us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.413m 1.054ms 1 1 100.00
rom_ctrl_tl_intg_err 38.230s 3.153ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.413m 1.054ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.413m 1.054ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 28.650s 2.155ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 28.650s 2.155ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 28.650s 2.155ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 28.650s 2.155ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 28.650s 2.155ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.413m 1.054ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.413m 1.054ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.140s 238.454us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.140s 238.454us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.140s 238.454us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 38.230s 3.153ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 28.650s 2.155ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.350s 741.851us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 28.650s 2.155ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 28.650s 2.155ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 28.650s 2.155ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 14.640s 569.549us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.413m 1.054ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.897m 1.805ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00