ROM_CTRL/64KB Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 14.060s 303.071us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.740s 1.045ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.870s 605.444us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.940s 863.873us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.690s 414.793us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.620s 360.340us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.870s 605.444us 1 1 100.00
rom_ctrl_csr_aliasing 7.690s 414.793us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 8.650s 701.350us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.170s 454.720us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.180s 392.663us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 20.770s 1.101ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.050s 2.028ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.110s 254.713us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.850s 562.966us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.850s 562.966us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.740s 1.045ms 1 1 100.00
rom_ctrl_csr_rw 6.870s 605.444us 1 1 100.00
rom_ctrl_csr_aliasing 7.690s 414.793us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.810s 701.965us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.740s 1.045ms 1 1 100.00
rom_ctrl_csr_rw 6.870s 605.444us 1 1 100.00
rom_ctrl_csr_aliasing 7.690s 414.793us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.810s 701.965us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.770m 2.863ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 29.040s 1.062ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 4.644m 3.511ms 1 1 100.00
rom_ctrl_tl_intg_err 1.098m 842.424us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 4.644m 3.511ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 4.644m 3.511ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.770m 2.863ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.770m 2.863ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.770m 2.863ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.770m 2.863ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.770m 2.863ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 4.644m 3.511ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 4.644m 3.511ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 14.060s 303.071us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 14.060s 303.071us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 14.060s 303.071us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.098m 842.424us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.770m 2.863ms 1 1 100.00
rom_ctrl_kmac_err_chk 14.050s 2.028ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.770m 2.863ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.770m 2.863ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.770m 2.863ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 29.040s 1.062ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 4.644m 3.511ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.947m 7.319ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00