SPI_DEVICE/1R1W Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	3.006m	64.123ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.930s	80.787us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.320s	62.420us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.760s	611.462us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.270s	5.660ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.970s	103.682us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.320s	62.420us	1	1	100.00
		spi_device_csr_aliasing	16.270s	5.660ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.490s	11.888us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.130s	534.021us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.750s	45.269us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.610s	7.446us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.640s	3.581us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.320s	780.325us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.320s	780.325us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	6.400s	10.822ms	1	1	100.00
		spi_device_tpm_sts_read	1.550s	34.106us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	15.830s	5.004ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.780s	103.838us	1	1	100.00
		spi_device_flash_all	22.600s	4.205ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.660s	380.357us	1	1	100.00
		spi_device_flash_all	22.600s	4.205ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.660s	380.357us	1	1	100.00
		spi_device_flash_all	22.600s	4.205ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	22.600s	4.205ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	20.080s	3.505ms	1	1	100.00
		spi_device_flash_all	22.600s	4.205ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	20.080s	3.505ms	1	1	100.00
		spi_device_flash_all	22.600s	4.205ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	20.080s	3.505ms	1	1	100.00
		spi_device_flash_all	22.600s	4.205ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	20.080s	3.505ms	1	1	100.00
		spi_device_flash_all	22.600s	4.205ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	20.080s	3.505ms	1	1	100.00
		spi_device_flash_all	22.600s	4.205ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	15.480s	27.329ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	14.010s	18.176ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	14.010s	18.176ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	14.010s	18.176ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.650s	5.195ms	1	1	100.00
		spi_device_read_buffer_direct	3.020s	908.675us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	14.010s	18.176ms	1	1	100.00
		spi_device_flash_all	22.600s	4.205ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	22.600s	4.205ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	22.600s	4.205ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.760s	156.037us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.760s	156.037us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	3.006m	64.123ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	31.200s	3.207ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.613m	31.346ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.570s	44.959us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.590s	260.982us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.100s	780.492us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.100s	780.492us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.930s	80.787us	1	1	100.00
		spi_device_csr_rw	2.320s	62.420us	1	1	100.00
		spi_device_csr_aliasing	16.270s	5.660ms	1	1	100.00
		spi_device_same_csr_outstanding	3.890s	181.956us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.930s	80.787us	1	1	100.00
		spi_device_csr_rw	2.320s	62.420us	1	1	100.00
		spi_device_csr_aliasing	16.270s	5.660ms	1	1	100.00
		spi_device_same_csr_outstanding	3.890s	181.956us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.030s	375.934us	1	1	100.00
		spi_device_tl_intg_err	15.720s	3.334ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	15.720s	3.334ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	11.850s	7.641ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.66232022295082802158016613474788088287260562743367719352759655177254339082213
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4362937 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[47])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4362937 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4362937 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[943])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.104964272616260688132705653469653962610976418358440411304940068303129664760386
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    919136 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa8f1fa [101010001111000111111010] vs 0x0 [0])
        UVM_ERROR @    974136 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf50d8c [111101010000110110001100] vs 0x0 [0])
        UVM_ERROR @   1035136 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa45bc3 [101001000101101111000011] vs 0x0 [0])
        UVM_ERROR @   1104136 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5747bc [10101110100011110111100] vs 0x0 [0])
        UVM_ERROR @   1114136 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x25f839 [1001011111100000111001] vs 0x0 [0])