SPI_DEVICE/2P Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	26.280s	17.569ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.080s	73.809us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.670s	53.862us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.110s	4.495ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.740s	729.729us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.820s	309.251us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.670s	53.862us	1	1	100.00
		spi_device_csr_aliasing	11.740s	729.729us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.620s	43.491us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.770s	56.416us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.880s	37.962us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.850s	36.295us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.830s	18.696us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	2.250s	24.182us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.250s	24.182us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.440s	2.682ms	1	1	100.00
		spi_device_tpm_sts_read	1.720s	286.686us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	18.830s	10.139ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.930s	417.406us	1	1	100.00
		spi_device_flash_all	7.010s	1.311ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	16.780s	113.872ms	1	1	100.00
		spi_device_flash_all	7.010s	1.311ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	16.780s	113.872ms	1	1	100.00
		spi_device_flash_all	7.010s	1.311ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	7.010s	1.311ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.540s	2.176ms	1	1	100.00
		spi_device_flash_all	7.010s	1.311ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.540s	2.176ms	1	1	100.00
		spi_device_flash_all	7.010s	1.311ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.540s	2.176ms	1	1	100.00
		spi_device_flash_all	7.010s	1.311ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.540s	2.176ms	1	1	100.00
		spi_device_flash_all	7.010s	1.311ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.540s	2.176ms	1	1	100.00
		spi_device_flash_all	7.010s	1.311ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	12.750s	30.732ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	56.900s	10.566ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	56.900s	10.566ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	56.900s	10.566ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	12.430s	15.800ms	1	1	100.00
		spi_device_read_buffer_direct	3.690s	99.001us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	56.900s	10.566ms	1	1	100.00
		spi_device_flash_all	7.010s	1.311ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	7.010s	1.311ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	7.010s	1.311ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.630s	33.157us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.630s	33.157us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	26.280s	17.569ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	49.290s	6.917ms	1	1	100.00
V2	stress_all	spi_device_stress_all	38.170s	7.877ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.530s	37.173us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.620s	16.816us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.440s	675.429us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.440s	675.429us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.080s	73.809us	1	1	100.00
		spi_device_csr_rw	2.670s	53.862us	1	1	100.00
		spi_device_csr_aliasing	11.740s	729.729us	1	1	100.00
		spi_device_same_csr_outstanding	3.200s	222.627us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.080s	73.809us	1	1	100.00
		spi_device_csr_rw	2.670s	53.862us	1	1	100.00
		spi_device_csr_aliasing	11.740s	729.729us	1	1	100.00
		spi_device_same_csr_outstanding	3.200s	222.627us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.960s	476.698us	1	1	100.00
		spi_device_tl_intg_err	10.660s	198.240us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.660s	198.240us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.770s	68.020us	1	1	100.00
		TOTAL			33	33	100.00