| V1 |
smoke |
spi_host_smoke |
9.000s |
468.176us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
spi_host_csr_hw_reset |
4.000s |
45.249us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
spi_host_csr_rw |
4.000s |
119.279us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
spi_host_csr_bit_bash |
5.000s |
582.517us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
spi_host_csr_aliasing |
3.000s |
47.306us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
spi_host_csr_mem_rw_with_rand_reset |
3.000s |
202.994us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
spi_host_csr_rw |
4.000s |
119.279us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
3.000s |
47.306us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
spi_host_mem_walk |
3.000s |
37.578us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
spi_host_mem_partial_access |
4.000s |
100.217us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
performance |
spi_host_performance |
4.000s |
20.701us |
1 |
1 |
100.00 |
| V2 |
error_event_intr |
spi_host_overflow_underflow |
5.000s |
48.721us |
1 |
1 |
100.00 |
|
|
spi_host_error_cmd |
3.000s |
21.901us |
1 |
1 |
100.00 |
|
|
spi_host_event |
7.000s |
483.380us |
1 |
1 |
100.00 |
| V2 |
clock_rate |
spi_host_speed |
11.000s |
1.067ms |
1 |
1 |
100.00 |
| V2 |
speed |
spi_host_speed |
11.000s |
1.067ms |
1 |
1 |
100.00 |
| V2 |
chip_select_timing |
spi_host_speed |
11.000s |
1.067ms |
1 |
1 |
100.00 |
| V2 |
sw_reset |
spi_host_sw_reset |
1.417m |
3.758ms |
1 |
1 |
100.00 |
| V2 |
passthrough_mode |
spi_host_passthrough_mode |
4.000s |
28.467us |
1 |
1 |
100.00 |
| V2 |
cpol_cpha |
spi_host_speed |
11.000s |
1.067ms |
1 |
1 |
100.00 |
| V2 |
full_cycle |
spi_host_speed |
11.000s |
1.067ms |
1 |
1 |
100.00 |
| V2 |
duplex |
spi_host_smoke |
9.000s |
468.176us |
1 |
1 |
100.00 |
| V2 |
tx_rx_only |
spi_host_smoke |
9.000s |
468.176us |
1 |
1 |
100.00 |
| V2 |
stress_all |
spi_host_stress_all |
7.000s |
692.160us |
1 |
1 |
100.00 |
| V2 |
spien |
spi_host_spien |
20.000s |
3.035ms |
1 |
1 |
100.00 |
| V2 |
stall |
spi_host_status_stall |
1.383m |
15.791ms |
1 |
1 |
100.00 |
| V2 |
Idlecsbactive |
spi_host_idlecsbactive |
5.000s |
275.668us |
1 |
1 |
100.00 |
| V2 |
data_fifo_status |
spi_host_overflow_underflow |
5.000s |
48.721us |
1 |
1 |
100.00 |
| V2 |
alert_test |
spi_host_alert_test |
4.000s |
26.565us |
1 |
1 |
100.00 |
| V2 |
intr_test |
spi_host_intr_test |
3.000s |
17.141us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
spi_host_tl_errors |
4.000s |
72.659us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
spi_host_tl_errors |
4.000s |
72.659us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
spi_host_csr_hw_reset |
4.000s |
45.249us |
1 |
1 |
100.00 |
|
|
spi_host_csr_rw |
4.000s |
119.279us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
3.000s |
47.306us |
1 |
1 |
100.00 |
|
|
spi_host_same_csr_outstanding |
4.000s |
17.011us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
spi_host_csr_hw_reset |
4.000s |
45.249us |
1 |
1 |
100.00 |
|
|
spi_host_csr_rw |
4.000s |
119.279us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
3.000s |
47.306us |
1 |
1 |
100.00 |
|
|
spi_host_same_csr_outstanding |
4.000s |
17.011us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
15 |
15 |
100.00 |
| V2S |
tl_intg_err |
spi_host_tl_intg_err |
4.000s |
590.186us |
1 |
1 |
100.00 |
|
|
spi_host_sec_cm |
4.000s |
204.661us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
spi_host_tl_intg_err |
4.000s |
590.186us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
spi_host_upper_range_clkdiv |
5.033m |
36.488ms |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
26 |
26 |
100.00 |