SRAM_CTRL/MAIN Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	31.800s	807.279us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.580s	51.705us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.480s	28.026us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.990s	126.815us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.690s	66.011us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.050s	359.216us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.480s	28.026us	1	1	100.00
		sram_ctrl_csr_aliasing	1.690s	66.011us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.939m	7.076ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	54.750s	2.611ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.973m	27.812ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.067m	3.289ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	16.415m	251.425ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	36.680s	4.541ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.990s	2.442ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.688m	93.878ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.900s	1.782ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.814m	29.478ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	9.480s	2.787ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	38.840s	808.337us	1	1	100.00
		sram_ctrl_throughput_w_readback	10.030s	2.715ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.737m	3.179ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.410s	351.206us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	2.040m	44.794ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.680s	23.931us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.840s	680.217us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.840s	680.217us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.580s	51.705us	1	1	100.00
		sram_ctrl_csr_rw	1.480s	28.026us	1	1	100.00
		sram_ctrl_csr_aliasing	1.690s	66.011us	1	1	100.00
		sram_ctrl_same_csr_outstanding	2.020s	24.540us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.580s	51.705us	1	1	100.00
		sram_ctrl_csr_rw	1.480s	28.026us	1	1	100.00
		sram_ctrl_csr_aliasing	1.690s	66.011us	1	1	100.00
		sram_ctrl_same_csr_outstanding	2.020s	24.540us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.520s	15.405ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.870s	43.506us	0	1	0.00
		sram_ctrl_tl_intg_err	3.660s	290.251us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.870s	43.506us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.660s	290.251us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.737m	3.179ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.737m	3.179ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.480s	28.026us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.688m	93.878ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.688m	93.878ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.688m	93.878ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.990s	2.442ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.780s	693.513us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.520s	15.405ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.800s	4.722ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	31.800s	807.279us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	31.800s	807.279us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.688m	93.878ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.870s	43.506us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.990s	2.442ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.870s	43.506us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.870s	43.506us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	31.800s	807.279us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.870s	43.506us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	21.700s	4.289ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.81458627505490552238946441756243591533857422913479388306771313913421104811959
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  43505919 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  43505919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---