SRAM_CTRL/RET Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	6.200s	97.688us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.670s	40.548us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.630s	39.771us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.600s	474.738us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.870s	15.363us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.270s	36.657us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.630s	39.771us	1	1	100.00
		sram_ctrl_csr_aliasing	1.870s	15.363us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.950s	273.391us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.640s	337.803us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	9.673m	5.522ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.406m	5.991ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	18.190s	9.342ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.110m	4.826ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.580s	171.580us	1	1	100.00
V2	executable	sram_ctrl_executable	16.918m	15.143ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	25.540s	626.486us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.041m	19.141ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	24.700s	839.369us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	45.660s	503.586us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.002m	295.327us	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.706m	23.294ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.570s	103.492us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	8.274m	9.264ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.680s	110.938us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.360s	148.460us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.360s	148.460us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.670s	40.548us	1	1	100.00
		sram_ctrl_csr_rw	1.630s	39.771us	1	1	100.00
		sram_ctrl_csr_aliasing	1.870s	15.363us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.540s	18.385us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.670s	40.548us	1	1	100.00
		sram_ctrl_csr_rw	1.630s	39.771us	1	1	100.00
		sram_ctrl_csr_aliasing	1.870s	15.363us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.540s	18.385us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.340s	219.842us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.740s	7.824us	0	1	0.00
		sram_ctrl_tl_intg_err	2.690s	824.886us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.740s	7.824us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.690s	824.886us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.706m	23.294ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.706m	23.294ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.630s	39.771us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	16.918m	15.143ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	16.918m	15.143ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	16.918m	15.143ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.580s	171.580us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.800s	46.476us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.340s	219.842us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.960s	35.386us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	6.200s	97.688us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	6.200s	97.688us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	16.918m	15.143ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.740s	7.824us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.580s	171.580us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.740s	7.824us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.740s	7.824us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	6.200s	97.688us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.740s	7.824us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.753m	66.323ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.57619737901179023470311509399469007470569430954797200558072092457459754925805
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7824139 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7824139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---