SYSRST_CTRL Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	2.920s	2.132ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	2.750s	2.462ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.130s	2.418ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	3.290s	2.320ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	11.880s	6.028ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	3.730s	2.078ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	1.103m	38.987ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	5.480s	3.479ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	2.660s	2.090ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	3.730s	2.078ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	5.480s	3.479ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	4.912m	156.311ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	26.060s	13.240ms	0	1	0.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	8.730s	3.715ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	4.430s	5.611ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	6.420s	2.514ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	5.080s	2.028ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	4.830s	3.461ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.020s	2.613ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.870s	8.173ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.173m	36.847ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	1.102m	148.994ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	2.630s	2.026ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	2.630s	2.044ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	3.990s	2.523ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	3.990s	2.523ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	11.880s	6.028ms	1	1	100.00
		sysrst_ctrl_csr_rw	3.730s	2.078ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	5.480s	3.479ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	14.840s	5.040ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	11.880s	6.028ms	1	1	100.00
		sysrst_ctrl_csr_rw	3.730s	2.078ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	5.480s	3.479ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	14.840s	5.040ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.308m	42.015ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	42.490s	42.562ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	42.490s	42.562ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	12.130s	5.508ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-* has 1 failures:
  • Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

    • 0.sysrst_ctrl_combo_detect_with_pre_cond.99552188943938397310130977844597750438838906422094574011587094391681568897607
      Line 389, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

        UVM_ERROR @ 13240454564 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-4
        UVM_ERROR @ 13240454564 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-4
        UVM_INFO @ 13240454564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---