UART Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.850s	296.163us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.550s	154.117us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.650s	14.214us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.250s	448.130us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.660s	36.558us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.720s	32.454us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.650s	14.214us	1	1	100.00
		uart_csr_aliasing	1.660s	36.558us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	48.200s	34.858ms	1	1	100.00
V2	parity	uart_smoke	1.850s	296.163us	1	1	100.00
		uart_tx_rx	48.200s	34.858ms	1	1	100.00
V2	parity_error	uart_intr	16.450s	13.078ms	1	1	100.00
		uart_rx_parity_err	21.800s	19.529ms	1	1	100.00
V2	watermark	uart_tx_rx	48.200s	34.858ms	1	1	100.00
		uart_intr	16.450s	13.078ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.352m	177.433ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	50.860s	62.634ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.564m	202.171ms	1	1	100.00
V2	rx_frame_err	uart_intr	16.450s	13.078ms	1	1	100.00
V2	rx_break_err	uart_intr	16.450s	13.078ms	1	1	100.00
V2	rx_timeout	uart_intr	16.450s	13.078ms	1	1	100.00
V2	perf	uart_perf	4.371m	26.805ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.390s	1.457ms	1	1	100.00
V2	line_loopback	uart_loopback	3.390s	1.457ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	40.480s	29.744ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.500s	5.109ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.270s	1.465ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	6.960s	3.622ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	8.458m	102.256ms	1	1	100.00
V2	stress_all	uart_stress_all	1.138m	52.864ms	1	1	100.00
V2	alert_test	uart_alert_test	1.460s	21.683us	1	1	100.00
V2	intr_test	uart_intr_test	1.530s	13.131us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.560s	121.503us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.560s	121.503us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.550s	154.117us	1	1	100.00
		uart_csr_rw	1.650s	14.214us	1	1	100.00
		uart_csr_aliasing	1.660s	36.558us	1	1	100.00
		uart_same_csr_outstanding	1.530s	23.454us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.550s	154.117us	1	1	100.00
		uart_csr_rw	1.650s	14.214us	1	1	100.00
		uart_csr_aliasing	1.660s	36.558us	1	1	100.00
		uart_same_csr_outstanding	1.530s	23.454us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.630s	129.577us	1	1	100.00
		uart_tl_intg_err	1.890s	261.894us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.890s	261.894us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	24.840s	2.494ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.26695441576702476046952855654691978629132276282948808710830943731040384746433
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 168309268 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 168319268 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 168329268 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 348429268 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 348429268 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 0.uart_stress_all_with_rand_reset.103862357590442637057840101313364972449436487749858847049963682476137321178793
      Line 125, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1709468456 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1709468456 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_INFO @ 1778158154 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/309
        UVM_INFO @ 1888297095 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/309
        UVM_INFO @ 1994040062 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/309