CHIP Simulation Results

Thursday June 19 2025 20:25:23 UTC

GitHub Revision: 1215104

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.176m	2.301ms	1	1	100.00
		chip_sw_example_rom	56.160s	2.022ms	1	1	100.00
		chip_sw_example_manufacturer	1.506m	2.859ms	1	1	100.00
		chip_sw_example_concurrency	2.198m	2.990ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	4.404m	6.092ms	1	1	100.00
V1	csr_rw	chip_csr_rw	7.148m	6.602ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	9.525m	10.584ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	53.489m	33.078ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	4.285m	6.303ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	53.489m	33.078ms	1	1	100.00
		chip_csr_rw	7.148m	6.602ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.480s	48.857us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.090m	4.463ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.090m	4.463ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.090m	4.463ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.698m	4.250ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.698m	4.250ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.504m	4.559ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.549m	4.491ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.083m	4.252ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	4.860m	4.441ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	4.673m	3.727ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	11.153m	9.214ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.919m	5.327ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.919m	5.327ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.389m	2.632ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.391m	3.192ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.503m	4.040ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	4.604m	5.952ms	1	1	100.00
		chip_tap_straps_testunlock0	7.678m	7.740ms	1	1	100.00
		chip_tap_straps_rma	6.018m	6.655ms	1	1	100.00
		chip_tap_straps_prod	11.372m	10.943ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.825m	2.649ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.306m	8.093ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.880m	5.293ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.880m	5.293ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.852m	6.622ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	18.116m	15.209ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.100m	4.493ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.332m	6.299ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	50.799m	18.334ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.369m	3.037ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.888m	5.892ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.934m	2.910ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.213m	7.225ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.004m	2.960ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.439m	5.329ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.882m	2.617ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.698m	3.447ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	9.353m	9.026ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.763m	5.128ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.536m	2.483ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.763m	5.128ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.367m	3.476ms	1	1	100.00
		chip_sw_aes_smoketest	2.498m	2.922ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.221m	3.483ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.934m	2.976ms	1	1	100.00
		chip_sw_csrng_smoketest	2.895m	3.312ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.505m	3.964ms	1	1	100.00
		chip_sw_gpio_smoketest	2.819m	3.453ms	1	1	100.00
		chip_sw_hmac_smoketest	2.720m	2.873ms	1	1	100.00
		chip_sw_kmac_smoketest	2.432m	3.019ms	1	1	100.00
		chip_sw_otbn_smoketest	6.912m	5.218ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.009m	6.780ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.754m	6.509ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.843m	2.994ms	1	1	100.00
		chip_sw_rv_timer_smoketest	1.657m	2.988ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.913m	2.960ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.270m	3.278ms	1	1	100.00
		chip_sw_uart_smoketest	2.219m	2.771ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.933m	2.363ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.884m	5.203ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.936h	60.064ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	34.084m	15.596ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	13.032s		0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.456m	3.785ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.678m	3.321ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.767h	53.925ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.726h	57.025ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	52.890s	2.207ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	52.890s	2.207ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	53.489m	33.078ms	1	1	100.00
		chip_same_csr_outstanding	43.771m	29.738ms	1	1	100.00
		chip_csr_hw_reset	4.404m	6.092ms	1	1	100.00
		chip_csr_rw	7.148m	6.602ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	53.489m	33.078ms	1	1	100.00
		chip_same_csr_outstanding	43.771m	29.738ms	1	1	100.00
		chip_csr_hw_reset	4.404m	6.092ms	1	1	100.00
		chip_csr_rw	7.148m	6.602ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	50.940s	2.222ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.980s	52.918us	1	1	100.00
		xbar_smoke_large_delays	57.410s	7.903ms	1	1	100.00
		xbar_smoke_slow_rsp	47.860s	5.763ms	1	1	100.00
		xbar_random_zero_delays	10.520s	108.046us	1	1	100.00
		xbar_random_large_delays	2.190m	22.300ms	1	1	100.00
		xbar_random_slow_rsp	4.293m	29.958ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	26.000s	319.822us	1	1	100.00
		xbar_error_and_unmapped_addr	24.590s	1.048ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	8.740s	146.725us	1	1	100.00
		xbar_error_and_unmapped_addr	24.590s	1.048ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	31.220s	592.357us	1	1	100.00
		xbar_access_same_device_slow_rsp	9.719m	67.339ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	16.380s	309.351us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	12.460s	449.154us	1	1	100.00
		xbar_stress_all_with_error	3.654m	12.253ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.151m	1.522ms	1	1	100.00
		xbar_stress_all_with_reset_error	3.099m	2.922ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	34.084m	15.596ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	7.366m	8.540ms	0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	34.837m	14.783ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	16.797s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.716s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	13.908s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.137s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.967s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	15.060s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	14.158s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	14.305s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.840s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	13.860s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.766s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	18.068s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	13.055s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	15.309s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	13.014s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	14.874s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.580s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.671s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.142s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	16.618s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	14.428s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.890s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	13.236s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19.983s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	13.752s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.774s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.992s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.193s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	21.068s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	15.670s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	16.744s		0	1	0.00
		rom_e2e_asm_init_dev	18.446s		0	1	0.00
		rom_e2e_asm_init_prod	20.606s		0	1	0.00
		rom_e2e_asm_init_prod_end	20.526s		0	1	0.00
		rom_e2e_asm_init_rma	13.944s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	34.893m	14.996ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	34.842m	15.202ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	32.974m	15.099ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	37.115m	15.941ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.338m	35.048ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.338m	35.048ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.059m	2.885ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.369m	3.037ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.494m	3.007ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.916m	2.444ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	17.846m	9.671ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.378m	3.016ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.488m	5.917ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	4.960m	5.263ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	10.470m	5.592ms	1	1	100.00
		chip_plic_all_irqs_10	3.625m	3.400ms	1	1	100.00
		chip_plic_all_irqs_20	5.961m	4.591ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.466m	2.839ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	16.634m	12.983ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	2.799m	3.470ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.682m	2.432ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.809m	12.694ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	18.548m	8.931ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.982m	6.458ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.921m	8.497ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.821h	255.151ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.816m	3.700ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.009m	6.780ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.816m	3.700ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.358m	10.039ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.358m	10.039ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	2.802m	5.886ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.256m	5.157ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.929m	5.767ms	1	1	100.00
		chip_sw_aes_idle	2.916m	2.444ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.181m	2.523ms	1	1	100.00
		chip_sw_kmac_idle	2.235m	2.264ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	5.635m	5.059ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	5.127m	4.170ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.266m	3.929ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.726m	4.775ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	13.953m	13.078ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.975m	3.995ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	4.854m	4.643ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.530m	4.282ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.274m	3.764ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.251m	4.117ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.133m	5.241ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.852m	6.622ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	7.854m	11.458ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.530m	4.282ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.274m	3.764ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.100m	4.493ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.332m	6.299ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	50.799m	18.334ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.369m	3.037ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.888m	5.892ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.934m	2.910ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.213m	7.225ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.004m	2.960ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.439m	5.329ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.882m	2.617ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.420m	2.601ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.112m	4.704ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.259m	6.883ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	42.322m	23.941ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.400m	3.284ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.924m	2.927ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	12.059m	9.147ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.894m	3.195ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.652m	5.011ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	13.994m	24.670ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.814h	135.149ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.852m	6.622ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.145m	4.023ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.324m	3.069ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	4.960m	5.263ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	18.548m	8.931ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.026m	6.842ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.736m	2.415ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.424m	5.719ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.589m	2.935ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	41.048m	18.569ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.605m	2.650ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.983m	6.005ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.605m	2.650ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.026m	6.842ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.703m	3.619ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	15.395m	19.903ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.301m	5.531ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.332m	6.299ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.359m	4.430ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.100m	4.493ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	53.890m	43.933ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	15.395m	19.903ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.683m	3.017ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	20.382m	10.623ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.292m	5.154ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	53.890m	43.933ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.292m	5.154ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.292m	5.154ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.292m	5.154ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.292m	5.154ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	4.960m	5.263ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.492m	6.235ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.978m	5.306ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.407m	4.725ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.407m	4.725ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.487m	2.938ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.934m	2.910ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.181m	2.523ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.891m	3.199ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.339m	3.471ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.718m	5.205ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.059m	4.352ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.439m	4.450ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.419m	3.722ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	20.382m	10.623ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.213m	7.225ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	11.226m	7.955ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	17.846m	9.671ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	31.834m	11.046ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.301m	2.384ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.737m	2.586ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.004m	2.960ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	20.382m	10.623ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	6.041m	7.505ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.769m	3.000ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	16.762m	8.024ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.235m	2.264ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.488m	5.917ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	4.604m	5.952ms	1	1	100.00
		chip_tap_straps_rma	6.018m	6.655ms	1	1	100.00
		chip_tap_straps_prod	11.372m	10.943ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.611m	3.019ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	6.041m	7.505ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	6.041m	7.505ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	6.041m	7.505ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	11.084m	6.939ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.292m	5.154ms	1	1	100.00
		chip_sw_flash_rma_unlocked	53.890m	43.933ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.301m	3.290ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.940m	5.812ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.560m	7.357ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.187m	7.704ms	1	1	100.00
		chip_sw_lc_ctrl_transition	6.041m	7.505ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.382m	10.623ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	6.623m	8.884ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.740m	7.739ms	1	1	100.00
		chip_prim_tl_access	2.492m	6.235ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	7.854m	11.458ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.975m	3.995ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	4.854m	4.643ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.530m	4.282ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.274m	3.764ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.251m	4.117ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.133m	5.241ms	1	1	100.00
		chip_tap_straps_dev	4.604m	5.952ms	1	1	100.00
		chip_tap_straps_rma	6.018m	6.655ms	1	1	100.00
		chip_tap_straps_prod	11.372m	10.943ms	1	1	100.00
		chip_rv_dm_lc_disabled	6.343m	14.669ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	1.890m	3.007ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.244m	3.721ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.230m	4.003ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.707m	4.166ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	22.663m	27.149ms	1	1	100.00
		chip_rv_dm_lc_disabled	6.343m	14.669ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	59.813m	47.005ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	57.871m	47.217ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	8.803m	10.297ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	54.669m	47.597ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	22.663m	27.149ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.031m	2.532ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	57.400s	2.686ms	1	1	100.00
		rom_volatile_raw_unlock	36.832s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	49.117m	16.698ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	50.799m	18.334ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.929m	5.767ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.929m	5.767ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.929m	5.767ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.641m	2.995ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	6.041m	7.505ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	15.395m	19.903ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.641m	2.995ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.382m	10.623ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.660m	3.532ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.770m	3.484ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	15.395m	19.903ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.641m	2.995ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.382m	10.623ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.660m	3.532ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.770m	3.484ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	6.041m	7.505ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.711m	4.477ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.611m	3.019ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.301m	3.290ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.940m	5.812ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.560m	7.357ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.187m	7.704ms	1	1	100.00
		chip_sw_lc_ctrl_transition	6.041m	7.505ms	1	1	100.00
		chip_prim_tl_access	2.492m	6.235ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.492m	6.235ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.356m	8.960ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	2.978m	5.952ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	14.601m	24.842ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.276m	7.334ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.108m	9.359ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.946m	6.015ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.952m	22.515ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	13.894m	15.448ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.358m	10.039ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.464m	11.077ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.606m	4.285ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	2.978m	5.952ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	2.810m	3.498ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	23.318m	33.500ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.704m	5.506ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.863m	6.014ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.499m	20.031ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.759m	7.560ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	10.731m	9.140ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	26.457m	27.594ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.732m	2.760ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	4.960m	5.263ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	6.623m	8.884ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	6.623m	8.884ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	10.731m	9.140ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.499m	20.031ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.606m	4.285ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.009m	6.780ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.155m	3.808ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.644m	4.827ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	2.747m	3.399ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	16.634m	12.983ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.931m	3.124ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	4.960m	5.263ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.982m	6.458ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.358m	4.475ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.227m	4.296ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.545m	2.914ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.770m	3.484ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.644m	4.827ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.644m	4.827ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.363m	4.500ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.095m	13.948ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.155m	3.808ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.978m	4.718ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.009m	5.499ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.018m	6.655ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.343m	14.669ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	10.470m	5.592ms	1	1	100.00
		chip_plic_all_irqs_10	3.625m	3.400ms	1	1	100.00
		chip_plic_all_irqs_20	5.961m	4.591ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.921m	2.768ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	1.878m	3.233ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	34.084m	15.596ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.676m	5.283ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.747m	3.065ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.299m	3.270ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.165m	2.807ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.660m	3.532ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.439m	5.329ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.002m	7.313ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.169m	8.122ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.740m	7.739ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	4.960m	5.263ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.880m	5.293ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.759m	7.560ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	17.547m	21.933ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.115m	2.932ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.266m	3.831ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.155m	4.448ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	17.547m	21.933ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	17.547m	21.933ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	12.043m	11.983ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	12.043m	11.983ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.602m	6.645ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.338m	35.048ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.247m	3.201ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.869m	2.680ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.562m	3.927ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.266m	4.588ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.775m	8.260ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.173h	31.530ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	26.344m	12.114ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.189m	3.298ms	1	1	100.00
V2		TOTAL			226	275	82.18
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.920m	3.869ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.570m	2.392ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.280h	72.070ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.114m	3.681ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	15.706m	11.242ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.084m	11.870ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.108m	11.245ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	28.990s		0	1	0.00
		rom_e2e_jtag_inject_dev	46.855s		0	1	0.00
		rom_e2e_jtag_inject_rma	1.397m		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	16.252s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.891m	4.524ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.566m	2.670ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	18.113m	6.642ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	15.400m	7.622ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.284m	2.496ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.255m	5.257ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	54.520s	2.375ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.306m	5.257ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.277m	5.563ms	0	1	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.266m	4.293ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	10.731m	9.140ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	15.706m	11.242ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.084m	11.870ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.108m	11.245ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.201m	4.792ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	4.960m	5.263ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.321h	38.288ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.321h	38.288ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.994m	3.401ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.698m	4.250ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	47.134m	18.365ms	1	1	100.00
V3		TOTAL			17	23	73.91
	Unmapped tests	chip_sival_flash_info_access	2.685m	3.433ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.105m	5.645ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.006m	2.774ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.552m	2.926ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.990m	3.514ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	13.504s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.370m	2.736ms	1	1	100.00
		TOTAL			268	325	82.46

Failure Buckets

• Job returned non-zero exit code has 42 failures:

  • Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

    • 0.chip_sw_pwrmgr_sleep_wake_5_bug.32298675324989955951552143949285345830045379795413582698409441127376444872736
      Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

        Computing main repo mapping:
        Loading:
        Loading: 0 packages loaded
        WARNING: Target pattern parsing failed.
        ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
        ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
        INFO: Elapsed time: 2.917s
        INFO: 0 processes.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.18490981218237462000306169180756624574873750886006754776241127548614495775097
      Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

        Error in fail: Bitstream cache not initialized properly.
        ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:76:10: //hw/bitstream:cw310_mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (1 packages loaded, 26451 targets configured)
      
        ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
        INFO: Elapsed time: 5.008s, Critical Path: 0.02s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.30428052877823460149596372656273459801349116435253405401741233836375149730975
      Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

            File "/nightly/runs/opentitan/rules/bitstreams.bzl", line 70, column 13, in _bitstreams_repo_impl
                fail("Bitstream cache not initialized properly.")
        Error in fail: Bitstream cache not initialized properly.
        ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:76:10: //hw/bitstream:cw310_mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
        INFO: Elapsed time: 3.744s, Critical Path: 0.02s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test rom_e2e_boot_policy_valid_a_good_b_good_prod has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.34753010291283541342126912210417911974664817130951859022448318943806052394118
      Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log

            File "/nightly/runs/opentitan/rules/bitstreams.bzl", line 70, column 13, in _bitstreams_repo_impl
                fail("Bitstream cache not initialized properly.")
        Error in fail: Bitstream cache not initialized properly.
        ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:64:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
        INFO: Elapsed time: 3.490s, Critical Path: 0.02s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test rom_e2e_boot_policy_valid_a_good_b_good_prod_end has 1 failures.

    • 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.14894753679322494044296592603505691581640364898547069693698054638204134718211
      Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log

            File "/nightly/runs/opentitan/rules/bitstreams.bzl", line 70, column 13, in _bitstreams_repo_impl
                fail("Bitstream cache not initialized properly.")
        Error in fail: Bitstream cache not initialized properly.
        ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:64:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
        ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
        INFO: Elapsed time: 2.247s, Critical Path: 0.02s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • ... and 37 more tests.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:

  • Test chip_sw_spi_device_pass_through_collision has 1 failures.

    • 0.chip_sw_spi_device_pass_through_collision.93964674750344040076413238913584096222385345066355599221366544837626444091421
      Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_ERROR @ 3064.887322 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
        UVM_INFO @ 3064.887322 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@87491) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_sw_rstmgr_cpu_info has 1 failures.

    • 0.chip_sw_rstmgr_cpu_info.25590386836741009936929303739040065982600905675155910638677365736651599802087
      Line 466, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

        UVM_ERROR @ 4826.635790 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@87491) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 4826.635790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:

  • Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.

    • 0.chip_sw_sysrst_ctrl_ec_rst_l.96472799654291602038879148054146324179638405187685219628388085015115943131715
      Line 425, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log

        UVM_ERROR @ 11982.572648 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
        UVM_INFO @ 11982.572648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:

  • Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.

    • 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.8493847030603013679077769947920479017165970852976481408221839431386383782572
      Line 434, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log

        UVM_ERROR @ 35048.018234 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 35048.018234 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:

  • Test chip_sw_alert_test has 1 failures.

    • 0.chip_sw_alert_test.18948959363651820831251120362431528677626320748604575463303158556839112746177
      Line 433, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log

        UVM_ERROR @ 3015.939336 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
        UVM_INFO @ 3015.939336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:

  • Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.

    • 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.74076811620955937670533670352975430555746755176660138695613435161180817198146
      Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 2431.750680 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
        UVM_INFO @ 2431.750680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:

  • Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.

    • 0.chip_sw_csrng_fuse_en_sw_app_read_test.56143950862771782911908049892557605672749395566461621125304692061967214307934
      Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log

        UVM_ERROR @ 2414.577827 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
        UVM_INFO @ 2414.577827 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40015) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 0.chip_tl_errors.23590247176600795150662865557352597116171868963027594381601957908003230158393
      Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

        UVM_ERROR @ 2206.608704 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40015) { a_addr: 'h106dc  a_data: 'h7dd9443b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h4  a_user: 'h1ba5b  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 2206.608704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:

  • Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 1 failures.

    • 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.52758587799391582180585829724390265090296434224178418748338875546285148025414
      Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log

        UVM_ERROR @ 5562.816380 us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: @@@:0 = ErrorError
        UVM_INFO @ 5562.816380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:

  • Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.

    • 0.chip_sw_rv_core_ibex_lockstep_glitch.100607432958090184617591774893926897228808838177110282741821637045270441356481
      Line 426, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log

        UVM_FATAL @ 2392.305336 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
        UVM_INFO @ 2392.305336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:

  • Test chip_sw_power_idle_load has 1 failures.

    • 0.chip_sw_power_idle_load.4563295542270000130284836928103725921016483275669228963274447709387990534709
      Line 412, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log

        UVM_ERROR @ 3784.512000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
        UVM_INFO @ 3784.512000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:

  • Test chip_sw_power_sleep_load has 1 failures.

    • 0.chip_sw_power_sleep_load.64104367118778633819857296358646472418727980653359635735700428133920145894106
      Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log

        UVM_ERROR @ 3321.166000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
        UVM_INFO @ 3321.166000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:

  • Test chip_sw_ast_clk_rst_inputs has 1 failures.

    • 0.chip_sw_ast_clk_rst_inputs.30565034331740118393481511830488435151249254417678063423065255208441185221520
      Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log

        UVM_ERROR @ 15209.140108 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
        UVM_INFO @ 15209.140108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:

  • Test chip_sw_power_virus has 1 failures.

    • 0.chip_sw_power_virus.36832307960944381909679370251995343587253311413839520469727485188794341779354
      Line 475, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log

        UVM_ERROR @ 3680.963915 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
        UVM_INFO @ 3680.963915 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:

  • Test rom_e2e_shutdown_output has 1 failures.

    • 0.rom_e2e_shutdown_output.76080504084554450385210782253129689835402722797779837412555581456947646502902
      Line 474, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log

            Offending '(pend_req[h2d.a_source].pend == 0)'
        UVM_ERROR @ 8540.358792 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
        UVM_INFO @ 8540.358792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---