AES/MASKED Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: 05d0058

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	239.994us	0	1	0.00
V1	smoke	aes_smoke	3.000s	125.121us	0	1	0.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	123.598us	1	1	100.00
V1	csr_rw	aes_csr_rw	4.000s	87.585us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	4.000s	93.267us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	61.720us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	178.301us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	87.585us	1	1	100.00
		aes_csr_aliasing	4.000s	61.720us	1	1	100.00
V1		TOTAL			5	7	71.43
V2	algorithm	aes_smoke	3.000s	125.121us	0	1	0.00
		aes_config_error	4.000s	73.580us	0	1	0.00
		aes_stress	4.000s	170.521us	0	1	0.00
V2	key_length	aes_smoke	3.000s	125.121us	0	1	0.00
		aes_config_error	4.000s	73.580us	0	1	0.00
		aes_stress	4.000s	170.521us	0	1	0.00
V2	back2back	aes_stress	4.000s	170.521us	0	1	0.00
		aes_b2b	3.000s	66.021us	0	1	0.00
V2	backpressure	aes_stress	4.000s	170.521us	0	1	0.00
V2	multi_message	aes_smoke	3.000s	125.121us	0	1	0.00
		aes_config_error	4.000s	73.580us	0	1	0.00
		aes_stress	4.000s	170.521us	0	1	0.00
		aes_alert_reset	4.000s	86.613us	0	1	0.00
V2	failure_test	aes_man_cfg_err	3.000s	67.797us	0	1	0.00
		aes_config_error	4.000s	73.580us	0	1	0.00
		aes_alert_reset	4.000s	86.613us	0	1	0.00
V2	trigger_clear_test	aes_clear	4.000s	146.794us	0	1	0.00
V2	nist_test_vectors	aes_nist_vectors	3.000s	62.843us	0	1	0.00
V2	reset_recovery	aes_alert_reset	4.000s	86.613us	0	1	0.00
V2	stress	aes_stress	4.000s	170.521us	0	1	0.00
V2	sideload	aes_stress	4.000s	170.521us	0	1	0.00
		aes_sideload	4.000s	103.352us	0	1	0.00
V2	deinitialization	aes_deinit	3.000s	90.395us	0	1	0.00
V2	stress_all	aes_stress_all	4.000s	58.997us	0	1	0.00
V2	alert_test	aes_alert_test	4.000s	55.313us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	3.000s	68.606us	0	1	0.00
V2	tl_d_illegal_access	aes_tl_errors	3.000s	68.606us	0	1	0.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	123.598us	1	1	100.00
		aes_csr_rw	4.000s	87.585us	1	1	100.00
		aes_csr_aliasing	4.000s	61.720us	1	1	100.00
		aes_same_csr_outstanding	3.000s	69.301us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	123.598us	1	1	100.00
		aes_csr_rw	4.000s	87.585us	1	1	100.00
		aes_csr_aliasing	4.000s	61.720us	1	1	100.00
		aes_same_csr_outstanding	3.000s	69.301us	1	1	100.00
V2		TOTAL			2	13	15.38
V2S	reseeding	aes_reseed	4.000s	74.260us	0	1	0.00
V2S	fault_inject	aes_fi	3.000s	69.595us	0	1	0.00
		aes_control_fi	4.000s	139.045us	0	1	0.00
		aes_cipher_fi	4.000s	107.859us	0	1	0.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	815.367us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	815.367us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	815.367us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	815.367us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	58.323us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	4.000s	120.288us	1	1	100.00
		aes_tl_intg_err	3.000s	379.996us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	379.996us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	86.613us	0	1	0.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	815.367us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	125.121us	0	1	0.00
		aes_stress	4.000s	170.521us	0	1	0.00
		aes_alert_reset	4.000s	86.613us	0	1	0.00
		aes_core_fi	4.000s	131.694us	0	1	0.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	815.367us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	109.814us	0	1	0.00
		aes_stress	4.000s	170.521us	0	1	0.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	170.521us	0	1	0.00
		aes_sideload	4.000s	103.352us	0	1	0.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	109.814us	0	1	0.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	109.814us	0	1	0.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	109.814us	0	1	0.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	109.814us	0	1	0.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	109.814us	0	1	0.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	170.521us	0	1	0.00
V2S	sec_cm_key_masking	aes_stress	4.000s	170.521us	0	1	0.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	69.595us	0	1	0.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	69.595us	0	1	0.00
		aes_control_fi	4.000s	139.045us	0	1	0.00
		aes_cipher_fi	4.000s	107.859us	0	1	0.00
		aes_ctr_fi	4.000s	80.223us	0	1	0.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	69.595us	0	1	0.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	69.595us	0	1	0.00
		aes_control_fi	4.000s	139.045us	0	1	0.00
		aes_cipher_fi	4.000s	107.859us	0	1	0.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	4.000s	107.859us	0	1	0.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	69.595us	0	1	0.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	69.595us	0	1	0.00
		aes_control_fi	4.000s	139.045us	0	1	0.00
		aes_ctr_fi	4.000s	80.223us	0	1	0.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	69.595us	0	1	0.00
		aes_control_fi	4.000s	139.045us	0	1	0.00
		aes_cipher_fi	4.000s	107.859us	0	1	0.00
		aes_ctr_fi	4.000s	80.223us	0	1	0.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	86.613us	0	1	0.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	69.595us	0	1	0.00
		aes_control_fi	4.000s	139.045us	0	1	0.00
		aes_cipher_fi	4.000s	107.859us	0	1	0.00
		aes_ctr_fi	4.000s	80.223us	0	1	0.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	69.595us	0	1	0.00
		aes_control_fi	4.000s	139.045us	0	1	0.00
		aes_cipher_fi	4.000s	107.859us	0	1	0.00
		aes_ctr_fi	4.000s	80.223us	0	1	0.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	69.595us	0	1	0.00
		aes_control_fi	4.000s	139.045us	0	1	0.00
		aes_ctr_fi	4.000s	80.223us	0	1	0.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	69.595us	0	1	0.00
		aes_control_fi	4.000s	139.045us	0	1	0.00
		aes_cipher_fi	4.000s	107.859us	0	1	0.00
V2S		TOTAL			4	11	36.36
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.000s	98.072us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			11	32	34.38

Failure Buckets

• UVM_FATAL (aes_scoreboard.sv:714) scoreboard [scoreboard] has 21 failures:

  • Test aes_wake_up has 1 failures.

    • 0.aes_wake_up.63173373765946301679444110511085845975677372596486701889898824190771511129319
      Line 664, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_wake_up/latest/run.log

        UVM_FATAL @ 239993889 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
             ----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
             ----| Expected:           1
             ----| Seen:               2
             ----| Expected corrupted: 0
      

  • Test aes_nist_vectors has 1 failures.

    • 0.aes_nist_vectors.102237483936674330019649222178368540789551579746932959446137378295038751094463
      Line 1608, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_nist_vectors/latest/run.log

        UVM_FATAL @  62843460 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
             ----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
             ----| Expected:           1
             ----| Seen:               2
             ----| Expected corrupted: 0
      

  • Test aes_deinit has 1 failures.

    • 0.aes_deinit.11138814301659117540205404272323530317690249610922698406039842713709537399223
      Line 1310, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_deinit/latest/run.log

        UVM_FATAL @  90395489 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
             ----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
             ----| Expected:           1
             ----| Seen:               2
             ----| Expected corrupted: 0
      

  • Test aes_man_cfg_err has 1 failures.

    • 0.aes_man_cfg_err.57197432473118981886778068280653206520612187316236281933360413913824087059247
      Line 1266, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_man_cfg_err/latest/run.log

        UVM_FATAL @  67796972 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
             ----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
             ----| Expected:           1
             ----| Seen:               2
             ----| Expected corrupted: 0
      

  • Test aes_readability has 1 failures.

    • 0.aes_readability.29656548581405619438855234836484861249186063390400108419896323280201216055027
      Line 804, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_readability/latest/run.log

        UVM_FATAL @ 109814228 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
             ----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
             ----| Expected:           1
             ----| Seen:               2
             ----| Expected corrupted: 0
      

  • ... and 16 more tests.