05d0058| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 3.000s | 90.251us | 0 | 1 | 0.00 |
| V1 | smoke | aes_smoke | 4.000s | 83.294us | 0 | 1 | 0.00 |
| V1 | csr_hw_reset | aes_csr_hw_reset | 3.000s | 53.494us | 1 | 1 | 100.00 |
| V1 | csr_rw | aes_csr_rw | 3.000s | 83.068us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | aes_csr_bit_bash | 3.000s | 75.617us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | aes_csr_aliasing | 3.000s | 84.615us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 4.000s | 86.998us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 3.000s | 83.068us | 1 | 1 | 100.00 |
| aes_csr_aliasing | 3.000s | 84.615us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 7 | 71.43 | |||
| V2 | algorithm | aes_smoke | 4.000s | 83.294us | 0 | 1 | 0.00 |
| aes_config_error | 4.000s | 69.431us | 0 | 1 | 0.00 | ||
| aes_stress | 4.000s | 65.289us | 0 | 1 | 0.00 | ||
| V2 | key_length | aes_smoke | 4.000s | 83.294us | 0 | 1 | 0.00 |
| aes_config_error | 4.000s | 69.431us | 0 | 1 | 0.00 | ||
| aes_stress | 4.000s | 65.289us | 0 | 1 | 0.00 | ||
| V2 | back2back | aes_stress | 4.000s | 65.289us | 0 | 1 | 0.00 |
| aes_b2b | 4.000s | 80.558us | 0 | 1 | 0.00 | ||
| V2 | backpressure | aes_stress | 4.000s | 65.289us | 0 | 1 | 0.00 |
| V2 | multi_message | aes_smoke | 4.000s | 83.294us | 0 | 1 | 0.00 |
| aes_config_error | 4.000s | 69.431us | 0 | 1 | 0.00 | ||
| aes_stress | 4.000s | 65.289us | 0 | 1 | 0.00 | ||
| aes_alert_reset | 4.000s | 130.426us | 0 | 1 | 0.00 | ||
| V2 | failure_test | aes_man_cfg_err | 4.000s | 73.458us | 0 | 1 | 0.00 |
| aes_config_error | 4.000s | 69.431us | 0 | 1 | 0.00 | ||
| aes_alert_reset | 4.000s | 130.426us | 0 | 1 | 0.00 | ||
| V2 | trigger_clear_test | aes_clear | 4.000s | 93.723us | 0 | 1 | 0.00 |
| V2 | nist_test_vectors | aes_nist_vectors | 4.000s | 65.371us | 0 | 1 | 0.00 |
| V2 | reset_recovery | aes_alert_reset | 4.000s | 130.426us | 0 | 1 | 0.00 |
| V2 | stress | aes_stress | 4.000s | 65.289us | 0 | 1 | 0.00 |
| V2 | sideload | aes_stress | 4.000s | 65.289us | 0 | 1 | 0.00 |
| aes_sideload | 5.000s | 156.556us | 0 | 1 | 0.00 | ||
| V2 | deinitialization | aes_deinit | 4.000s | 88.287us | 0 | 1 | 0.00 |
| V2 | stress_all | aes_stress_all | 3.000s | 71.456us | 0 | 1 | 0.00 |
| V2 | alert_test | aes_alert_test | 4.000s | 77.325us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | aes_tl_errors | 3.000s | 76.462us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | aes_tl_errors | 3.000s | 76.462us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 3.000s | 53.494us | 1 | 1 | 100.00 |
| aes_csr_rw | 3.000s | 83.068us | 1 | 1 | 100.00 | ||
| aes_csr_aliasing | 3.000s | 84.615us | 1 | 1 | 100.00 | ||
| aes_same_csr_outstanding | 3.000s | 60.820us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 3.000s | 53.494us | 1 | 1 | 100.00 |
| aes_csr_rw | 3.000s | 83.068us | 1 | 1 | 100.00 | ||
| aes_csr_aliasing | 3.000s | 84.615us | 1 | 1 | 100.00 | ||
| aes_same_csr_outstanding | 3.000s | 60.820us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 2 | 13 | 15.38 | |||
| V2S | reseeding | aes_reseed | 3.000s | 115.423us | 0 | 1 | 0.00 |
| V2S | fault_inject | aes_fi | 4.000s | 75.175us | 0 | 1 | 0.00 |
| aes_control_fi | 3.000s | 91.524us | 0 | 1 | 0.00 | ||
| aes_cipher_fi | 3.000s | 78.209us | 0 | 1 | 0.00 | ||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 3.000s | 127.649us | 1 | 1 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 3.000s | 127.649us | 1 | 1 | 100.00 |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 3.000s | 127.649us | 1 | 1 | 100.00 |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 3.000s | 127.649us | 1 | 1 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 3.000s | 52.987us | 1 | 1 | 100.00 |
| V2S | tl_intg_err | aes_sec_cm | 4.000s | 99.434us | 1 | 1 | 100.00 |
| aes_tl_intg_err | 3.000s | 82.741us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 3.000s | 82.741us | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 4.000s | 130.426us | 0 | 1 | 0.00 |
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 3.000s | 127.649us | 1 | 1 | 100.00 |
| V2S | sec_cm_main_config_sparse | aes_smoke | 4.000s | 83.294us | 0 | 1 | 0.00 |
| aes_stress | 4.000s | 65.289us | 0 | 1 | 0.00 | ||
| aes_alert_reset | 4.000s | 130.426us | 0 | 1 | 0.00 | ||
| aes_core_fi | 3.000s | 75.722us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 3.000s | 127.649us | 1 | 1 | 100.00 |
| V2S | sec_cm_aux_config_regwen | aes_readability | 4.000s | 62.776us | 0 | 1 | 0.00 |
| aes_stress | 4.000s | 65.289us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_key_sideload | aes_stress | 4.000s | 65.289us | 0 | 1 | 0.00 |
| aes_sideload | 5.000s | 156.556us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 4.000s | 62.776us | 0 | 1 | 0.00 |
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 4.000s | 62.776us | 0 | 1 | 0.00 |
| V2S | sec_cm_key_sec_wipe | aes_readability | 4.000s | 62.776us | 0 | 1 | 0.00 |
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 4.000s | 62.776us | 0 | 1 | 0.00 |
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 4.000s | 62.776us | 0 | 1 | 0.00 |
| V2S | sec_cm_data_reg_key_sca | aes_stress | 4.000s | 65.289us | 0 | 1 | 0.00 |
| V2S | sec_cm_key_masking | aes_stress | 4.000s | 65.289us | 0 | 1 | 0.00 |
| V2S | sec_cm_main_fsm_sparse | aes_fi | 4.000s | 75.175us | 0 | 1 | 0.00 |
| V2S | sec_cm_main_fsm_redun | aes_fi | 4.000s | 75.175us | 0 | 1 | 0.00 |
| aes_control_fi | 3.000s | 91.524us | 0 | 1 | 0.00 | ||
| aes_cipher_fi | 3.000s | 78.209us | 0 | 1 | 0.00 | ||
| aes_ctr_fi | 3.000s | 86.136us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 4.000s | 75.175us | 0 | 1 | 0.00 |
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 4.000s | 75.175us | 0 | 1 | 0.00 |
| aes_control_fi | 3.000s | 91.524us | 0 | 1 | 0.00 | ||
| aes_cipher_fi | 3.000s | 78.209us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 3.000s | 78.209us | 0 | 1 | 0.00 |
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 4.000s | 75.175us | 0 | 1 | 0.00 |
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 4.000s | 75.175us | 0 | 1 | 0.00 |
| aes_control_fi | 3.000s | 91.524us | 0 | 1 | 0.00 | ||
| aes_ctr_fi | 3.000s | 86.136us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_ctrl_sparse | aes_fi | 4.000s | 75.175us | 0 | 1 | 0.00 |
| aes_control_fi | 3.000s | 91.524us | 0 | 1 | 0.00 | ||
| aes_cipher_fi | 3.000s | 78.209us | 0 | 1 | 0.00 | ||
| aes_ctr_fi | 3.000s | 86.136us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 4.000s | 130.426us | 0 | 1 | 0.00 |
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 4.000s | 75.175us | 0 | 1 | 0.00 |
| aes_control_fi | 3.000s | 91.524us | 0 | 1 | 0.00 | ||
| aes_cipher_fi | 3.000s | 78.209us | 0 | 1 | 0.00 | ||
| aes_ctr_fi | 3.000s | 86.136us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 4.000s | 75.175us | 0 | 1 | 0.00 |
| aes_control_fi | 3.000s | 91.524us | 0 | 1 | 0.00 | ||
| aes_cipher_fi | 3.000s | 78.209us | 0 | 1 | 0.00 | ||
| aes_ctr_fi | 3.000s | 86.136us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 4.000s | 75.175us | 0 | 1 | 0.00 |
| aes_control_fi | 3.000s | 91.524us | 0 | 1 | 0.00 | ||
| aes_ctr_fi | 3.000s | 86.136us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 4.000s | 75.175us | 0 | 1 | 0.00 |
| aes_control_fi | 3.000s | 91.524us | 0 | 1 | 0.00 | ||
| aes_cipher_fi | 3.000s | 78.209us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 4 | 11 | 36.36 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 3.000s | 89.831us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 11 | 32 | 34.38 |
UVM_FATAL (aes_scoreboard.sv:714) scoreboard [scoreboard] has 21 failures:
Test aes_wake_up has 1 failures.
0.aes_wake_up.73108123620850103157538295887014977590748946537122393734837817007793577043550
Line 440, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_wake_up/latest/run.log
UVM_FATAL @ 90250714 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
Test aes_nist_vectors has 1 failures.
0.aes_nist_vectors.58238919925495840309791334560003172713722664543991810009256716166034122546913
Line 464, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_nist_vectors/latest/run.log
UVM_FATAL @ 65370714 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
Test aes_deinit has 1 failures.
0.aes_deinit.70539101357753424929754263772634264096496285378633827182574453600030734184024
Line 470, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_deinit/latest/run.log
UVM_FATAL @ 88286926 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
Test aes_man_cfg_err has 1 failures.
0.aes_man_cfg_err.53835254210363885169683663958015813150095237580258896674232869203942198748156
Line 442, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
UVM_FATAL @ 73457559 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
Test aes_readability has 1 failures.
0.aes_readability.23194655161566392122978812754072228989540409626058066423869520981777232261110
Line 578, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_readability/latest/run.log
UVM_FATAL @ 62776201 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
----| Expected: 1
----| Seen: 2
----| Expected corrupted: 0
... and 16 more tests.