EDN Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: 05d0058

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.790s	13.482us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.660s	12.343us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.630s	38.570us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	0.690s	40.473us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	0.680s	19.673us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.650s	36.101us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.630s	38.570us	1	1	100.00
		edn_csr_aliasing	0.680s	19.673us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	0.730s	17.105us	1	1	100.00
V2	csrng_commands	edn_genbits	0.730s	17.105us	1	1	100.00
V2	genbits	edn_genbits	0.730s	17.105us	1	1	100.00
V2	interrupts	edn_intr	0.610s	76.914us	1	1	100.00
V2	alerts	edn_alert	0.690s	36.372us	1	1	100.00
V2	errs	edn_err	0.690s	42.505us	1	1	100.00
V2	disable	edn_disable	0.720s	13.516us	1	1	100.00
		edn_disable_auto_req_mode	0.770s	12.992us	1	1	100.00
V2	stress_all	edn_stress_all	0.700s	18.618us	1	1	100.00
V2	intr_test	edn_intr_test	0.770s	12.492us	1	1	100.00
V2	alert_test	edn_alert_test	0.780s	67.155us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	0.680s	21.641us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	0.680s	21.641us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.660s	12.343us	1	1	100.00
		edn_csr_rw	0.630s	38.570us	1	1	100.00
		edn_csr_aliasing	0.680s	19.673us	1	1	100.00
		edn_same_csr_outstanding	0.700s	134.739us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.660s	12.343us	1	1	100.00
		edn_csr_rw	0.630s	38.570us	1	1	100.00
		edn_csr_aliasing	0.680s	19.673us	1	1	100.00
		edn_same_csr_outstanding	0.700s	134.739us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	0.750s	12.781us	1	1	100.00
		edn_tl_intg_err	0.710s	26.224us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.780s	25.619us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.690s	36.372us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	0.750s	12.781us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	0.750s	12.781us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	0.750s	12.781us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	0.750s	12.781us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.690s	36.372us	1	1	100.00
		edn_sec_cm	0.750s	12.781us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.690s	36.372us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	0.710s	26.224us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	0.750s	23.331us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00