HMAC Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: 05d0058

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	0.550s	4.692us	0	1	0.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.570s	1.199us	0	1	0.00
V1	csr_rw	hmac_csr_rw	0.540s	4.877us	0	1	0.00
V1	csr_bit_bash	hmac_csr_bit_bash	0.500s	4.635us	0	1	0.00
V1	csr_aliasing	hmac_csr_aliasing	0.530s	1.404us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	0.530s	3.968us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.540s	4.877us	0	1	0.00
		hmac_csr_aliasing	0.530s	1.404us	0	1	0.00
V1		TOTAL			0	6	0.00
V2	long_msg	hmac_long_msg	0.530s	4.694us	0	1	0.00
V2	back_pressure	hmac_back_pressure	0.560s	2.204us	0	1	0.00
V2	test_vectors	hmac_test_sha256_vectors	1.460s	1.327us	0	1	0.00
		hmac_test_sha384_vectors	1.380s	2.071us	0	1	0.00
		hmac_test_sha512_vectors	1.450s	1.166us	0	1	0.00
		hmac_test_hmac256_vectors	1.340s	1.277us	0	1	0.00
		hmac_test_hmac384_vectors	1.350s	997.243ns	0	1	0.00
		hmac_test_hmac512_vectors	1.330s	1.282us	0	1	0.00
V2	burst_wr	hmac_burst_wr	0.520s	1.489us	0	1	0.00
V2	datapath_stress	hmac_datapath_stress	0.510s	3.256us	0	1	0.00
V2	error	hmac_error	0.530s	5.388us	0	1	0.00
V2	wipe_secret	hmac_wipe_secret	0.540s	2.071us	0	1	0.00
V2	save_and_restore	hmac_smoke	0.550s	4.692us	0	1	0.00
		hmac_long_msg	0.530s	4.694us	0	1	0.00
		hmac_back_pressure	0.560s	2.204us	0	1	0.00
		hmac_datapath_stress	0.510s	3.256us	0	1	0.00
		hmac_burst_wr	0.520s	1.489us	0	1	0.00
		hmac_stress_all	0.570s	2.016us	0	1	0.00
V2	fifo_empty_status_interrupt	hmac_smoke	0.550s	4.692us	0	1	0.00
		hmac_long_msg	0.530s	4.694us	0	1	0.00
		hmac_back_pressure	0.560s	2.204us	0	1	0.00
		hmac_datapath_stress	0.510s	3.256us	0	1	0.00
		hmac_wipe_secret	0.540s	2.071us	0	1	0.00
		hmac_test_sha256_vectors	1.460s	1.327us	0	1	0.00
		hmac_test_sha384_vectors	1.380s	2.071us	0	1	0.00
		hmac_test_sha512_vectors	1.450s	1.166us	0	1	0.00
		hmac_test_hmac256_vectors	1.340s	1.277us	0	1	0.00
		hmac_test_hmac384_vectors	1.350s	997.243ns	0	1	0.00
		hmac_test_hmac512_vectors	1.330s	1.282us	0	1	0.00
V2	wide_digest_configurable_key_length	hmac_smoke	0.550s	4.692us	0	1	0.00
		hmac_long_msg	0.530s	4.694us	0	1	0.00
		hmac_back_pressure	0.560s	2.204us	0	1	0.00
		hmac_datapath_stress	0.510s	3.256us	0	1	0.00
		hmac_burst_wr	0.520s	1.489us	0	1	0.00
		hmac_error	0.530s	5.388us	0	1	0.00
		hmac_wipe_secret	0.540s	2.071us	0	1	0.00
		hmac_test_sha256_vectors	1.460s	1.327us	0	1	0.00
		hmac_test_sha384_vectors	1.380s	2.071us	0	1	0.00
		hmac_test_sha512_vectors	1.450s	1.166us	0	1	0.00
		hmac_test_hmac256_vectors	1.340s	1.277us	0	1	0.00
		hmac_test_hmac384_vectors	1.350s	997.243ns	0	1	0.00
		hmac_test_hmac512_vectors	1.330s	1.282us	0	1	0.00
		hmac_stress_all	0.570s	2.016us	0	1	0.00
V2	stress_all	hmac_stress_all	0.570s	2.016us	0	1	0.00
V2	alert_test	hmac_alert_test	0.520s	2.022us	0	1	0.00
V2	intr_test	hmac_intr_test	0.550s	4.758us	0	1	0.00
V2	tl_d_oob_addr_access	hmac_tl_errors	0.590s	4.344us	0	1	0.00
V2	tl_d_illegal_access	hmac_tl_errors	0.590s	4.344us	0	1	0.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.570s	1.199us	0	1	0.00
		hmac_csr_rw	0.540s	4.877us	0	1	0.00
		hmac_csr_aliasing	0.530s	1.404us	0	1	0.00
		hmac_same_csr_outstanding	0.530s	1.822us	0	1	0.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.570s	1.199us	0	1	0.00
		hmac_csr_rw	0.540s	4.877us	0	1	0.00
		hmac_csr_aliasing	0.530s	1.404us	0	1	0.00
		hmac_same_csr_outstanding	0.530s	1.822us	0	1	0.00
V2		TOTAL			0	17	0.00
V2S	tl_intg_err	hmac_sec_cm	0.530s	2.844us	0	1	0.00
		hmac_tl_intg_err	0.500s	6.021us	0	1	0.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	0.500s	6.021us	0	1	0.00
V2S		TOTAL			0	2	0.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	0.550s	4.692us	0	1	0.00
V3	stress_reset	hmac_stress_reset	0.530s	23.690us	0	1	0.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	0.520s	1.057us	0	1	0.00
V3		TOTAL			0	2	0.00
	Unmapped tests	hmac_directed	0.510s	7.881us	0	1	0.00
		TOTAL			0	28	0.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class! has 28 failures:

  • Test hmac_smoke has 1 failures.

    • 0.hmac_smoke.68725248801430587736257051697720311773636288271145654746508332117712115975997
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_smoke/latest/run.log

        UVM_FATAL @   4692056 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   4692056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test hmac_long_msg has 1 failures.

    • 0.hmac_long_msg.75076678688785632724797931911918285929460075758489150160878689375663189026222
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_long_msg/latest/run.log

        UVM_FATAL @   4694281 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   4694281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test hmac_stress_reset has 1 failures.

    • 0.hmac_stress_reset.42670521072340332230623386479230207245092950696543828489234209913544494447377
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_stress_reset/latest/run.log

        UVM_FATAL @  23690072 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @  23690072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test hmac_back_pressure has 1 failures.

    • 0.hmac_back_pressure.15461897584978274155113455618283113555563361445058263360130703455786662043896
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_back_pressure/latest/run.log

        UVM_FATAL @   2204122 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   2204122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test hmac_datapath_stress has 1 failures.

    • 0.hmac_datapath_stress.102858731339512015804975403307000803737462287498430884839593609551754669799251
      Line 72, in log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_datapath_stress/latest/run.log

        UVM_FATAL @   3255850 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [hmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   3255850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 23 more tests.