I2C Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: 05d0058

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	0.620s	3.044us	0	1	0.00
V1	target_smoke	i2c_target_smoke	0.570s	3.927us	0	1	0.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.540s	16.760us	0	1	0.00
V1	csr_rw	i2c_csr_rw	0.520s	3.009us	0	1	0.00
V1	csr_bit_bash	i2c_csr_bit_bash	0.560s	1.129us	0	1	0.00
V1	csr_aliasing	i2c_csr_aliasing	0.590s	4.312us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.530s	6.403us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.520s	3.009us	0	1	0.00
		i2c_csr_aliasing	0.590s	4.312us	0	1	0.00
V1		TOTAL			0	7	0.00
V2	host_error_intr	i2c_host_error_intr	0.520s	1.792us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	0.600s	6.437us	0	1	0.00
V2	host_maxperf	i2c_host_perf	0.500s	4.223us	0	1	0.00
V2	host_override	i2c_host_override	0.530s	662.407ns	0	1	0.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	0.550s	795.973ns	0	1	0.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	0.580s	805.006ns	0	1	0.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.540s	736.224ns	0	1	0.00
		i2c_host_fifo_fmt_empty	0.540s	916.112ns	0	1	0.00
		i2c_host_fifo_reset_rx	0.510s	6.250us	0	1	0.00
V2	host_fifo_full	i2c_host_fifo_full	0.540s	1.005us	0	1	0.00
V2	host_timeout	i2c_host_stretch_timeout	0.550s	3.294us	0	1	0.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.560s	6.919us	0	1	0.00
V2	target_glitch	i2c_target_glitch	0.520s	1.850us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	0.620s	915.164ns	0	1	0.00
V2	target_maxperf	i2c_target_perf	0.600s	780.278ns	0	1	0.00
V2	target_fifo_empty	i2c_target_stress_rd	0.560s	2.488us	0	1	0.00
		i2c_target_intr_smoke	0.560s	4.926us	0	1	0.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.580s	1.695us	0	1	0.00
		i2c_target_fifo_reset_tx	0.600s	1.739us	0	1	0.00
V2	target_fifo_full	i2c_target_stress_wr	0.520s	4.373us	0	1	0.00
		i2c_target_stress_rd	0.560s	2.488us	0	1	0.00
		i2c_target_intr_stress_wr	0.620s	4.157us	0	1	0.00
V2	target_timeout	i2c_target_timeout	0.630s	4.265us	0	1	0.00
V2	target_clock_stretch	i2c_target_stretch	0.580s	3.374us	0	1	0.00
V2	bad_address	i2c_target_bad_addr	0.590s	3.628us	0	1	0.00
V2	target_mode_glitch	i2c_target_hrst	0.600s	914.491ns	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	0.570s	4.044us	0	1	0.00
		i2c_target_fifo_watermarks_tx	0.550s	3.467us	0	1	0.00
V2	host_mode_config_perf	i2c_host_perf	0.500s	4.223us	0	1	0.00
		i2c_host_perf_precise	0.530s	10.058us	0	1	0.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	0.550s	3.294us	0	1	0.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	0.590s	2.192us	0	1	0.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	0.540s	4.192us	0	1	0.00
		i2c_target_nack_acqfull_addr	0.590s	3.872us	0	1	0.00
		i2c_target_nack_txstretch	0.530s	6.717us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	0.600s	3.671us	0	1	0.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	0.530s	13.286us	0	1	0.00
V2	alert_test	i2c_alert_test	0.540s	4.744us	0	1	0.00
V2	intr_test	i2c_intr_test	0.540s	3.371us	0	1	0.00
V2	tl_d_oob_addr_access	i2c_tl_errors	0.540s	4.128us	0	1	0.00
V2	tl_d_illegal_access	i2c_tl_errors	0.540s	4.128us	0	1	0.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.540s	16.760us	0	1	0.00
		i2c_csr_rw	0.520s	3.009us	0	1	0.00
		i2c_csr_aliasing	0.590s	4.312us	0	1	0.00
		i2c_same_csr_outstanding	0.600s	2.911us	0	1	0.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.540s	16.760us	0	1	0.00
		i2c_csr_rw	0.520s	3.009us	0	1	0.00
		i2c_csr_aliasing	0.590s	4.312us	0	1	0.00
		i2c_same_csr_outstanding	0.600s	2.911us	0	1	0.00
V2		TOTAL			0	38	0.00
V2S	tl_intg_err	i2c_tl_intg_err	0.560s	3.693us	0	1	0.00
		i2c_sec_cm	0.580s	4.741us	0	1	0.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	0.560s	3.693us	0	1	0.00
V2S		TOTAL			0	2	0.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	0.600s	3.003us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	0.670s	10.385us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	0.610s	2.233us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			0	50	0.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [i2c_base_vseq] Need to override this when you extend from this class! has 50 failures:

  • Test i2c_host_smoke has 1 failures.

    • 0.i2c_host_smoke.94011483479636653087990278371380549585176375105158935226026664121306282323047
      Line 73, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_smoke/latest/run.log

        UVM_FATAL @   3044202 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [i2c_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   3044202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_override has 1 failures.

    • 0.i2c_host_override.72735630193938176760924234585180075984135416739386246619812808788100899048354
      Line 73, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_override/latest/run.log

        UVM_FATAL @    662407 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [i2c_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @    662407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_fifo_watermark has 1 failures.

    • 0.i2c_host_fifo_watermark.51161293454410579980259778085791859367830364208577711179704191493191010651982
      Line 73, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_fifo_watermark/latest/run.log

        UVM_FATAL @    795973 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [i2c_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @    795973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_fifo_overflow has 1 failures.

    • 0.i2c_host_fifo_overflow.79467484147437354430189335883589091786708429199863131368408798953687712084426
      Line 73, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest/run.log

        UVM_FATAL @    805006 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [i2c_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @    805006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_fifo_reset_fmt has 1 failures.

    • 0.i2c_host_fifo_reset_fmt.50102656293017251206909974446845487146527493362970631254454337975273873200423
      Line 73, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_fifo_reset_fmt/latest/run.log

        UVM_FATAL @    736224 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [i2c_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @    736224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 45 more tests.