KEYMGR Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: 05d0058

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	0.760s	13.730us	0	1	0.00
V1	random	keymgr_random	0.650s	5.769us	0	1	0.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.590s	5.606us	0	1	0.00
V1	csr_rw	keymgr_csr_rw	0.610s	2.766us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	0.580s	7.338us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	0.650s	3.038us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	0.610s	945.363ns	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.610s	2.766us	0	1	0.00
		keymgr_csr_aliasing	0.650s	3.038us	0	1	0.00
V1		TOTAL			0	7	0.00
V2	cfgen_during_op	keymgr_cfg_regwen	0.660s	4.364us	0	1	0.00
V2	sideload	keymgr_sideload	0.560s	5.382us	0	1	0.00
		keymgr_sideload_kmac	0.580s	6.731us	0	1	0.00
		keymgr_sideload_aes	0.840s	51.329us	0	1	0.00
		keymgr_sideload_otbn	0.610s	2.805us	0	1	0.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	0.680s	28.568us	0	1	0.00
V2	lc_disable	keymgr_lc_disable	0.570s	6.539us	0	1	0.00
V2	kmac_error_response	keymgr_kmac_rsp_err	0.590s	2.616us	0	1	0.00
V2	invalid_sw_input	keymgr_sw_invalid_input	0.590s	3.454us	0	1	0.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	0.880s	16.302us	0	1	0.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	0.610s	4.203us	0	1	0.00
V2	stress_all	keymgr_stress_all	0.620s	4.924us	0	1	0.00
V2	intr_test	keymgr_intr_test	0.600s	2.443us	0	1	0.00
V2	alert_test	keymgr_alert_test	0.590s	2.095us	0	1	0.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	0.550s	1.320us	0	1	0.00
V2	tl_d_illegal_access	keymgr_tl_errors	0.550s	1.320us	0	1	0.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.590s	5.606us	0	1	0.00
		keymgr_csr_rw	0.610s	2.766us	0	1	0.00
		keymgr_csr_aliasing	0.650s	3.038us	0	1	0.00
		keymgr_same_csr_outstanding	0.590s	1.600us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.590s	5.606us	0	1	0.00
		keymgr_csr_rw	0.610s	2.766us	0	1	0.00
		keymgr_csr_aliasing	0.650s	3.038us	0	1	0.00
		keymgr_same_csr_outstanding	0.590s	1.600us	0	1	0.00
V2		TOTAL			0	16	0.00
V2S	sec_cm_additional_check	keymgr_sec_cm	0.620s	4.493us	0	1	0.00
V2S	tl_intg_err	keymgr_sec_cm	0.620s	4.493us	0	1	0.00
		keymgr_tl_intg_err	0.590s	2.705us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	0.630s	2.445us	0	1	0.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	0.630s	2.445us	0	1	0.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	0.630s	2.445us	0	1	0.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	0.630s	2.445us	0	1	0.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	0.540s	1.627us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	0.620s	4.493us	0	1	0.00
V2S	prim_fsm_check	keymgr_sec_cm	0.620s	4.493us	0	1	0.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	0.590s	2.705us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	0.630s	2.445us	0	1	0.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	0.660s	4.364us	0	1	0.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	0.650s	5.769us	0	1	0.00
		keymgr_csr_rw	0.610s	2.766us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	0.650s	5.769us	0	1	0.00
		keymgr_csr_rw	0.610s	2.766us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	0.650s	5.769us	0	1	0.00
		keymgr_csr_rw	0.610s	2.766us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	0.570s	6.539us	0	1	0.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	0.880s	16.302us	0	1	0.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	0.880s	16.302us	0	1	0.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	0.650s	5.769us	0	1	0.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	0.830s	13.934us	0	1	0.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	0.620s	4.493us	0	1	0.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	0.620s	4.493us	0	1	0.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	0.620s	4.493us	0	1	0.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	0.590s	4.203us	0	1	0.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	0.570s	6.539us	0	1	0.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	0.620s	4.493us	0	1	0.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	0.620s	4.493us	0	1	0.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	0.620s	4.493us	0	1	0.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	0.590s	4.203us	0	1	0.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	0.590s	4.203us	0	1	0.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	0.620s	4.493us	0	1	0.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	0.590s	4.203us	0	1	0.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	0.620s	4.493us	0	1	0.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	0.590s	4.203us	0	1	0.00
V2S		TOTAL			0	6	0.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	0.600s	1.910us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			0	30	0.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class! has 25 failures:

  • Test keymgr_smoke has 1 failures.

    • 0.keymgr_smoke.47870543782347794170993883359792838032702973577403761059604459904690617597188
      Line 95, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_smoke/latest/run.log

        UVM_FATAL @  13729748 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @  13729748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_sideload has 1 failures.

    • 0.keymgr_sideload.103932452312039748242100417660106830230096743131330059551814853712638800700494
      Line 75, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sideload/latest/run.log

        UVM_FATAL @   5381862 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   5381862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_sideload_kmac has 1 failures.

    • 0.keymgr_sideload_kmac.83345286701953692525390696907655707092446422079337260738613840919333790731480
      Line 75, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest/run.log

        UVM_FATAL @   6730790 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   6730790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_sideload_aes has 1 failures.

    • 0.keymgr_sideload_aes.76156882850860919412871701918139356825819322532517408569852805683142892260477
      Line 116, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sideload_aes/latest/run.log

        UVM_FATAL @  51329104 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @  51329104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_sideload_otbn has 1 failures.

    • 0.keymgr_sideload_otbn.91824133750233367463290999188952806677130027703604072747189705754268703580618
      Line 96, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest/run.log

        UVM_FATAL @   2805374 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [keymgr_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   2805374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 20 more tests.

• UVM_ERROR (keymgr_base_vseq.sv:199) [keymgr_base_vseq] Check failed gmv(ral.op_status.status) == exp_status (* [] vs * [])` has 5 failures:

  • Test keymgr_sec_cm has 1 failures.

    • 0.keymgr_sec_cm.67948213216263061320272040679580879548351154945141520128749392996656663527940
      Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sec_cm/latest/run.log

        UVM_ERROR @   4493347 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
        UVM_INFO @   4493347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.4427419585339145641931552985988947284215469723751844977688259548154848306359
      Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @   1627185 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
        UVM_INFO @   1627185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.65304244971998156084733233293434959504071295888289577780535378681813968730083
      Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

        UVM_ERROR @   2705194 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
        UVM_INFO @   2705194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_hw_reset has 1 failures.

    • 0.keymgr_csr_hw_reset.87630814877203447231050522216200348860318103946519514235934020521049588668735
      Line 76, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest/run.log

        UVM_ERROR @   5606268 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
        UVM_INFO @   5606268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.85611551747804365565337811399948091238449216128961916282557636850426517042953
      Line 75, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

        UVM_ERROR @   7338376 ps: (keymgr_base_vseq.sv:199) [uvm_test_top.env.virtual_sequencer.keymgr_base_vseq] Check failed `gmv(ral.op_status.status) == exp_status (0 [0x0] vs 3 [0x3])
        UVM_INFO @   7338376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---