05d0058| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 0.710s | 29.613us | 0 | 1 | 0.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 0.760s | 4.018us | 0 | 1 | 0.00 |
| V1 | csr_rw | kmac_csr_rw | 0.660s | 1.686us | 0 | 1 | 0.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 0.620s | 5.363us | 0 | 1 | 0.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 0.650s | 1.094us | 0 | 1 | 0.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 0.610s | 5.903us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 0.660s | 1.686us | 0 | 1 | 0.00 |
| kmac_csr_aliasing | 0.650s | 1.094us | 0 | 1 | 0.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.660s | 2.216us | 0 | 1 | 0.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 0.630s | 3.276us | 0 | 1 | 0.00 |
| V1 | TOTAL | 0 | 8 | 0.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 0.720s | 5.852us | 0 | 1 | 0.00 |
| V2 | burst_write | kmac_burst_write | 0.680s | 9.740us | 0 | 1 | 0.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 0.700s | 4.914us | 0 | 1 | 0.00 |
| kmac_test_vectors_sha3_256 | 0.670s | 3.118us | 0 | 1 | 0.00 | ||
| kmac_test_vectors_sha3_384 | 0.690s | 4.631us | 0 | 1 | 0.00 | ||
| kmac_test_vectors_sha3_512 | 0.660s | 4.769us | 0 | 1 | 0.00 | ||
| kmac_test_vectors_shake_128 | 0.660s | 2.584us | 0 | 1 | 0.00 | ||
| kmac_test_vectors_shake_256 | 0.660s | 7.219us | 0 | 1 | 0.00 | ||
| kmac_test_vectors_kmac | 0.650s | 1.343us | 0 | 1 | 0.00 | ||
| kmac_test_vectors_kmac_xof | 0.650s | 1.722us | 0 | 1 | 0.00 | ||
| V2 | sideload | kmac_sideload | 0.750s | 13.945us | 0 | 1 | 0.00 |
| V2 | app | kmac_app | 0.650s | 7.773us | 0 | 1 | 0.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 0.650s | 2.937us | 0 | 1 | 0.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 0.680s | 5.535us | 0 | 1 | 0.00 |
| V2 | error | kmac_error | 0.650s | 2.300us | 0 | 1 | 0.00 |
| V2 | key_error | kmac_key_error | 0.630s | 5.554us | 0 | 1 | 0.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 0.690s | 1.924us | 0 | 1 | 0.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 0.660s | 4.316us | 0 | 1 | 0.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 0.640s | 5.408us | 0 | 1 | 0.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 0.640s | 6.808us | 0 | 1 | 0.00 |
| V2 | lc_escalation | kmac_lc_escalation | 0.670s | 4.778us | 0 | 1 | 0.00 |
| V2 | stress_all | kmac_stress_all | 0.670s | 21.930us | 0 | 1 | 0.00 |
| V2 | intr_test | kmac_intr_test | 0.660s | 11.151us | 0 | 1 | 0.00 |
| V2 | alert_test | kmac_alert_test | 0.670s | 4.516us | 0 | 1 | 0.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 0.660s | 5.258us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 0.660s | 5.258us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 0.760s | 4.018us | 0 | 1 | 0.00 |
| kmac_csr_rw | 0.660s | 1.686us | 0 | 1 | 0.00 | ||
| kmac_csr_aliasing | 0.650s | 1.094us | 0 | 1 | 0.00 | ||
| kmac_same_csr_outstanding | 0.620s | 2.366us | 0 | 1 | 0.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 0.760s | 4.018us | 0 | 1 | 0.00 |
| kmac_csr_rw | 0.660s | 1.686us | 0 | 1 | 0.00 | ||
| kmac_csr_aliasing | 0.650s | 1.094us | 0 | 1 | 0.00 | ||
| kmac_same_csr_outstanding | 0.620s | 2.366us | 0 | 1 | 0.00 | ||
| V2 | TOTAL | 0 | 26 | 0.00 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 0.670s | 1.937us | 0 | 1 | 0.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 0.670s | 1.937us | 0 | 1 | 0.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 0.670s | 1.937us | 0 | 1 | 0.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 0.670s | 1.937us | 0 | 1 | 0.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 0.690s | 6.714us | 0 | 1 | 0.00 |
| V2S | tl_intg_err | kmac_sec_cm | 0.730s | 3.812us | 0 | 1 | 0.00 |
| kmac_tl_intg_err | 0.640s | 2.785us | 0 | 1 | 0.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 0.640s | 2.785us | 0 | 1 | 0.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 0.670s | 4.778us | 0 | 1 | 0.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 0.710s | 29.613us | 0 | 1 | 0.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 0.750s | 13.945us | 0 | 1 | 0.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 0.670s | 1.937us | 0 | 1 | 0.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 0.730s | 3.812us | 0 | 1 | 0.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 0.730s | 3.812us | 0 | 1 | 0.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 0.730s | 3.812us | 0 | 1 | 0.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 0.710s | 29.613us | 0 | 1 | 0.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 0.670s | 4.778us | 0 | 1 | 0.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 0.730s | 3.812us | 0 | 1 | 0.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 0.710s | 2.383us | 0 | 1 | 0.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 0.710s | 29.613us | 0 | 1 | 0.00 |
| V2S | TOTAL | 0 | 5 | 0.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 0.640s | 2.804us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 0 | 40 | 0.00 |
UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [kmac_base_vseq] Need to override this when you extend from this class! has 27 failures:
Test kmac_burst_write has 1 failures.
0.kmac_burst_write.54086071464504847125989154090323197425163003927389841430150196427148294706665
Line 72, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_burst_write/latest/run.log
UVM_FATAL @ 9739676 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [kmac_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 9739676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_sha3_256 has 1 failures.
0.kmac_test_vectors_sha3_256.34897652691574516146532090123715612647340751575001965247234383170046505660420
Line 72, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest/run.log
UVM_FATAL @ 3118174 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [kmac_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 3118174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_sha3_512 has 1 failures.
0.kmac_test_vectors_sha3_512.91614152667407063832276375488349557347898505746674528243173741307828143743663
Line 72, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest/run.log
UVM_FATAL @ 4769402 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [kmac_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 4769402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_shake_128 has 1 failures.
0.kmac_test_vectors_shake_128.93213904643404871557864025977099248843283210414925638426210374343591032392486
Line 72, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log
UVM_FATAL @ 2583821 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [kmac_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 2583821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_app has 1 failures.
0.kmac_app.112103185427978541541517226366404145446057619043929872375099716259918670469970
Line 72, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_app/latest/run.log
UVM_FATAL @ 7772766 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [kmac_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 7772766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more tests.
Error-[FCIBH] Illegal bin hit has 13 failures:
Test kmac_smoke has 1 failures.
0.kmac_smoke.90155557625556864471206880508240076468067331535845522285389577843969997627486
Line 73, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_smoke/latest/run.log
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv, 301
kmac_env_pkg, "kmac_env_pkg::kmac_env_cov::error_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 29612618 ps, Illegal
state bin il of coverpoint kmac_err_code in covergroup
Test kmac_long_msg_and_output has 1 failures.
0.kmac_long_msg_and_output.79073624869087745867508011716126710358211979214090005361378525731043232648718
Line 73, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest/run.log
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv, 301
kmac_env_pkg, "kmac_env_pkg::kmac_env_cov::error_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 5851576 ps, Illegal state
bin il of coverpoint kmac_err_code in covergroup
Test kmac_sideload has 1 failures.
0.kmac_sideload.56313179173538995483708347639704650155245897022937805849178427792016231556456
Line 73, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_sideload/latest/run.log
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv, 301
kmac_env_pkg, "kmac_env_pkg::kmac_env_cov::error_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 13945329 ps, Illegal
state bin il of coverpoint kmac_err_code in covergroup
Test kmac_sideload_invalid has 1 failures.
0.kmac_sideload_invalid.70912501941611309720443398399964635107554062685609295180163056884661407991406
Line 73, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv, 301
kmac_env_pkg, "kmac_env_pkg::kmac_env_cov::error_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1923553 ps, Illegal state
bin il of coverpoint kmac_err_code in covergroup
Test kmac_test_vectors_sha3_224 has 1 failures.
0.kmac_test_vectors_sha3_224.39079124084456396112654130179660707633670748144080296332232036874313341983621
Line 73, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest/run.log
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv, 301
kmac_env_pkg, "kmac_env_pkg::kmac_env_cov::error_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 4914176 ps, Illegal state
bin il of coverpoint kmac_err_code in covergroup
... and 8 more tests.