KMAC/UNMASKED Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: 05d0058

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	0.700s	1.492us	0	1	0.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.660s	3.110us	0	1	0.00
V1	csr_rw	kmac_csr_rw	0.630s	2.439us	0	1	0.00
V1	csr_bit_bash	kmac_csr_bit_bash	0.660s	1.950us	0	1	0.00
V1	csr_aliasing	kmac_csr_aliasing	0.640s	6.450us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	0.610s	6.802us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.630s	2.439us	0	1	0.00
		kmac_csr_aliasing	0.640s	6.450us	0	1	0.00
V1	mem_walk	kmac_mem_walk	0.620s	6.515us	0	1	0.00
V1	mem_partial_access	kmac_mem_partial_access	0.600s	3.896us	0	1	0.00
V1		TOTAL			0	8	0.00
V2	long_msg_and_output	kmac_long_msg_and_output	0.710s	1.168us	0	1	0.00
V2	burst_write	kmac_burst_write	0.650s	2.263us	0	1	0.00
V2	test_vectors	kmac_test_vectors_sha3_224	0.640s	1.444us	0	1	0.00
		kmac_test_vectors_sha3_256	0.670s	3.816us	0	1	0.00
		kmac_test_vectors_sha3_384	0.640s	14.663us	0	1	0.00
		kmac_test_vectors_sha3_512	0.640s	1.538us	0	1	0.00
		kmac_test_vectors_shake_128	0.680s	12.875us	0	1	0.00
		kmac_test_vectors_shake_256	0.680s	18.359us	0	1	0.00
		kmac_test_vectors_kmac	0.670s	1.716us	0	1	0.00
		kmac_test_vectors_kmac_xof	0.650s	12.799us	0	1	0.00
V2	sideload	kmac_sideload	0.650s	5.232us	0	1	0.00
V2	app	kmac_app	0.630s	5.090us	0	1	0.00
V2	app_with_partial_data	kmac_app_with_partial_data	0.630s	6.929us	0	1	0.00
V2	entropy_refresh	kmac_entropy_refresh	0.670s	41.917us	0	1	0.00
V2	error	kmac_error	0.630s	1.756us	0	1	0.00
V2	key_error	kmac_key_error	0.670s	7.625us	0	1	0.00
V2	sideload_invalid	kmac_sideload_invalid	0.620s	7.779us	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	0.630s	4.302us	0	1	0.00
V2	entropy_mode_error	kmac_entropy_mode_error	0.630s	3.102us	0	1	0.00
V2	entropy_ready_error	kmac_entropy_ready_error	0.640s	4.016us	0	1	0.00
V2	lc_escalation	kmac_lc_escalation	0.620s	3.150us	0	1	0.00
V2	stress_all	kmac_stress_all	0.630s	7.481us	0	1	0.00
V2	intr_test	kmac_intr_test	0.620s	3.760us	0	1	0.00
V2	alert_test	kmac_alert_test	0.570s	1.326us	0	1	0.00
V2	tl_d_oob_addr_access	kmac_tl_errors	0.590s	3.937us	0	1	0.00
V2	tl_d_illegal_access	kmac_tl_errors	0.590s	3.937us	0	1	0.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.660s	3.110us	0	1	0.00
		kmac_csr_rw	0.630s	2.439us	0	1	0.00
		kmac_csr_aliasing	0.640s	6.450us	0	1	0.00
		kmac_same_csr_outstanding	0.630s	2.372us	0	1	0.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.660s	3.110us	0	1	0.00
		kmac_csr_rw	0.630s	2.439us	0	1	0.00
		kmac_csr_aliasing	0.640s	6.450us	0	1	0.00
		kmac_same_csr_outstanding	0.630s	2.372us	0	1	0.00
V2		TOTAL			0	26	0.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	0.640s	7.734us	0	1	0.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	0.640s	7.734us	0	1	0.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	0.640s	7.734us	0	1	0.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	0.640s	7.734us	0	1	0.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	0.620s	4.221us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	0.590s	8.252us	0	1	0.00
		kmac_tl_intg_err	0.590s	5.334us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	0.590s	5.334us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	0.620s	3.150us	0	1	0.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	0.700s	1.492us	0	1	0.00
V2S	sec_cm_key_sideload	kmac_sideload	0.650s	5.232us	0	1	0.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	0.640s	7.734us	0	1	0.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	0.590s	8.252us	0	1	0.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	0.590s	8.252us	0	1	0.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	0.590s	8.252us	0	1	0.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	0.700s	1.492us	0	1	0.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	0.620s	3.150us	0	1	0.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	0.590s	8.252us	0	1	0.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	0.660s	1.303us	0	1	0.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	0.700s	1.492us	0	1	0.00
V2S		TOTAL			0	5	0.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	0.600s	4.043us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			0	40	0.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [kmac_base_vseq] Need to override this when you extend from this class! has 40 failures:

  • Test kmac_smoke has 1 failures.

    • 0.kmac_smoke.87037163207306503621595323142732253096354837944926577301234180014803596175203
      Line 72, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_smoke/latest/run.log

        UVM_FATAL @   1491514 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [kmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1491514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_long_msg_and_output has 1 failures.

    • 0.kmac_long_msg_and_output.101985077002047700264707721565077314986895902676096427052009260894054196154311
      Line 72, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest/run.log

        UVM_FATAL @   1167789 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [kmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1167789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_sideload has 1 failures.

    • 0.kmac_sideload.95358099088520992262936151561003838924733762471999193525734251487721911735763
      Line 72, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload/latest/run.log

        UVM_FATAL @   5231770 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [kmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   5231770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.87131167817413984244987446726876675526615236111766970330032606508188540774308
      Line 72, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @   7779109 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [kmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   7779109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_burst_write has 1 failures.

    • 0.kmac_burst_write.47892815316232049609869066262708890920823475639836371132526036311916918194808
      Line 72, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest/run.log

        UVM_FATAL @   2263260 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [kmac_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   2263260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 35 more tests.