OTBN Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: 05d0058

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	4.000s	3.636us	0	1	0.00
V1	single_binary	otbn_single	4.000s	958.178ns	0	1	0.00
V1	csr_hw_reset	otbn_csr_hw_reset	3.000s	1.803us	0	1	0.00
V1	csr_rw	otbn_csr_rw	3.000s	1.775us	0	1	0.00
V1	csr_bit_bash	otbn_csr_bit_bash	3.000s	4.772us	0	1	0.00
V1	csr_aliasing	otbn_csr_aliasing	4.000s	940.520ns	0	1	0.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	4.000s	4.487us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	3.000s	1.775us	0	1	0.00
		otbn_csr_aliasing	4.000s	940.520ns	0	1	0.00
V1	mem_walk	otbn_mem_walk	4.000s	5.975us	0	1	0.00
V1	mem_partial_access	otbn_mem_partial_access	4.000s	3.406us	0	1	0.00
V1		TOTAL			0	9	0.00
V2	reset_recovery	otbn_reset	4.000s	1.740us	0	1	0.00
V2	multi_error	otbn_multi_err	4.000s	935.410ns	0	1	0.00
V2	back_to_back	otbn_multi	4.000s	9.110us	0	1	0.00
V2	stress_all	otbn_stress_all	6.000s	11.537us	0	1	0.00
V2	lc_escalation	otbn_escalate	5.000s	1.527us	0	1	0.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	4.000s	2.164us	0	1	0.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	4.000s	2.746us	0	1	0.00
V2	alert_test	otbn_alert_test	6.000s	4.870us	0	1	0.00
V2	intr_test	otbn_intr_test	4.000s	21.795us	0	1	0.00
V2	tl_d_oob_addr_access	otbn_tl_errors	4.000s	3.128us	0	1	0.00
V2	tl_d_illegal_access	otbn_tl_errors	4.000s	3.128us	0	1	0.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	3.000s	1.803us	0	1	0.00
		otbn_csr_rw	3.000s	1.775us	0	1	0.00
		otbn_csr_aliasing	4.000s	940.520ns	0	1	0.00
		otbn_same_csr_outstanding	4.000s	3.758us	0	1	0.00
V2	tl_d_partial_access	otbn_csr_hw_reset	3.000s	1.803us	0	1	0.00
		otbn_csr_rw	3.000s	1.775us	0	1	0.00
		otbn_csr_aliasing	4.000s	940.520ns	0	1	0.00
		otbn_same_csr_outstanding	4.000s	3.758us	0	1	0.00
V2		TOTAL			0	11	0.00
V2S	mem_integrity	otbn_imem_err	5.000s	2.546us	0	1	0.00
		otbn_dmem_err	5.000s	3.987us	0	1	0.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	6.000s	15.328us	0	1	0.00
		otbn_controller_ispr_rdata_err	4.000s	1.206us	0	1	0.00
		otbn_mac_bignum_acc_err	4.000s	4.481us	0	1	0.00
		otbn_urnd_err	5.000s	2.364us	0	1	0.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	6.000s	14.919us	0	1	0.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	4.000s	1.448us	0	1	0.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	4.000s	2.046us	0	1	0.00
V2S	tl_intg_err	otbn_sec_cm	5.000s	3.785us	0	1	0.00
		otbn_tl_intg_err	4.000s	2.167us	0	1	0.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	3.000s	3.994us	0	1	0.00
V2S	prim_fsm_check	otbn_sec_cm	5.000s	3.785us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	5.000s	3.785us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	4.000s	3.636us	0	1	0.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	5.000s	3.987us	0	1	0.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	5.000s	2.546us	0	1	0.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	4.000s	2.167us	0	1	0.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	5.000s	1.527us	0	1	0.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	5.000s	2.546us	0	1	0.00
		otbn_dmem_err	5.000s	3.987us	0	1	0.00
		otbn_zero_state_err_urnd	4.000s	2.164us	0	1	0.00
		otbn_illegal_mem_acc	6.000s	14.919us	0	1	0.00
		otbn_sec_cm	5.000s	3.785us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.000s	3.785us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	4.000s	958.178ns	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	5.000s	2.546us	0	1	0.00
		otbn_dmem_err	5.000s	3.987us	0	1	0.00
		otbn_zero_state_err_urnd	4.000s	2.164us	0	1	0.00
		otbn_illegal_mem_acc	6.000s	14.919us	0	1	0.00
		otbn_sec_cm	5.000s	3.785us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.000s	3.785us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	5.000s	1.527us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	5.000s	2.546us	0	1	0.00
		otbn_dmem_err	5.000s	3.987us	0	1	0.00
		otbn_zero_state_err_urnd	4.000s	2.164us	0	1	0.00
		otbn_illegal_mem_acc	6.000s	14.919us	0	1	0.00
		otbn_sec_cm	5.000s	3.785us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.000s	3.785us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	4.000s	958.178ns	0	1	0.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	4.000s	2.399us	0	1	0.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	4.000s	4.519us	0	1	0.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	4.000s	6.318us	0	1	0.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	4.000s	6.318us	0	1	0.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	4.000s	2.735us	0	1	0.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.000s	3.785us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.000s	3.785us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	4.000s	972.756ns	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.000s	3.785us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.000s	3.785us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	5.000s	6.751us	0	1	0.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	5.000s	6.751us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	5.000s	2.974us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	4.000s	958.178ns	0	1	0.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	4.000s	958.178ns	0	1	0.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	4.000s	958.178ns	0	1	0.00
V2S	sec_cm_write_mem_integrity	otbn_multi	4.000s	9.110us	0	1	0.00
V2S	sec_cm_ctrl_flow_count	otbn_single	4.000s	958.178ns	0	1	0.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	4.000s	958.178ns	0	1	0.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	4.000s	1.960us	0	1	0.00
V2S	sec_cm_key_sideload	otbn_single	4.000s	958.178ns	0	1	0.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.000s	3.785us	0	1	0.00
V2S		TOTAL			0	20	0.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	4.000s	1.133us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			0	41	0.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [otbn_base_vseq] Need to override this when you extend from this class! has 41 failures:

  • Test otbn_smoke has 1 failures.

    • 0.otbn_smoke.17609533434159801734881484918774118768413451072180427282425093636920115224748
      Line 113, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest/run.log

        UVM_FATAL @   3636183 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [otbn_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   3636183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otbn_single has 1 failures.

    • 0.otbn_single.12691122401376230572360868519906909419149503910828951555779251357466455712897
      Line 113, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_single/latest/run.log

        UVM_FATAL @    958178 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [otbn_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @    958178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otbn_multi has 1 failures.

    • 0.otbn_multi.41148466034232095037280194428067003822598000381058866197575889268612404228172
      Line 143, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest/run.log

        UVM_FATAL @   9109968 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [otbn_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   9109968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otbn_reset has 1 failures.

    • 0.otbn_reset.66578372099113495159452838106713771404981690233060641207566486962651288011368
      Line 104, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_reset/latest/run.log

        UVM_FATAL @   1739840 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [otbn_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1739840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otbn_multi_err has 1 failures.

    • 0.otbn_multi_err.10473669263621432824854805629920736738975822062527410774847798807181511618210
      Line 192, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_multi_err/latest/run.log

        UVM_FATAL @    935410 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [otbn_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @    935410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 36 more tests.