PATTGEN Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: 05d0058

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 2.000s 0 1 0.00
V1 csr_hw_reset pattgen_csr_hw_reset 2.000s 0 1 0.00
V1 csr_rw pattgen_csr_rw 2.000s 0 1 0.00
V1 csr_bit_bash pattgen_csr_bit_bash 2.000s 0 1 0.00
V1 csr_aliasing pattgen_csr_aliasing 3.000s 0 1 0.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 3.000s 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 2.000s 0 1 0.00
pattgen_csr_aliasing 3.000s 0 1 0.00
V1 TOTAL 0 6 0.00
V2 perf pattgen_perf 2.000s 0 1 0.00
V2 cnt_rollover cnt_rollover 3.000s 0 1 0.00
V2 error pattgen_error 2.000s 0 1 0.00
V2 stress_all pattgen_stress_all 3.000s 0 1 0.00
V2 alert_test pattgen_alert_test 3.000s 0 1 0.00
V2 intr_test pattgen_intr_test 3.000s 0 1 0.00
V2 tl_d_oob_addr_access pattgen_tl_errors 4.000s 0 1 0.00
V2 tl_d_illegal_access pattgen_tl_errors 4.000s 0 1 0.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 2.000s 0 1 0.00
pattgen_csr_rw 2.000s 0 1 0.00
pattgen_csr_aliasing 3.000s 0 1 0.00
pattgen_same_csr_outstanding 3.000s 0 1 0.00
V2 tl_d_partial_access pattgen_csr_hw_reset 2.000s 0 1 0.00
pattgen_csr_rw 2.000s 0 1 0.00
pattgen_csr_aliasing 3.000s 0 1 0.00
pattgen_same_csr_outstanding 3.000s 0 1 0.00
V2 TOTAL 0 8 0.00
V2S tl_intg_err pattgen_tl_intg_err 3.000s 0 1 0.00
pattgen_sec_cm 3.000s 0 1 0.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 3.000s 0 1 0.00
V2S TOTAL 0 2 0.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 3.000s 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests pattgen_inactive_level 3.000s 0 1 0.00
TOTAL 0 18 0.00

Failure Buckets