ROM_CTRL/32KB Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: 05d0058

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.440s	2.940us	0	1	0.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	1.440s	1.047us	0	1	0.00
V1	csr_rw	rom_ctrl_csr_rw	1.440s	1.521us	0	1	0.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	1.490s	3.502us	0	1	0.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	1.430s	1.087us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	1.400s	3.348us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	1.440s	1.521us	0	1	0.00
		rom_ctrl_csr_aliasing	1.430s	1.087us	0	1	0.00
V1	mem_walk	rom_ctrl_mem_walk	1.400s	2.614us	0	1	0.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	1.460s	4.053us	0	1	0.00
V1		TOTAL			0	8	0.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	1.380s	4.254us	0	1	0.00
V2	stress_all	rom_ctrl_stress_all	1.490s	4.573us	0	1	0.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.350s	2.229us	0	1	0.00
V2	alert_test	rom_ctrl_alert_test	1.470s	13.526us	0	1	0.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	1.570s	1.083us	0	1	0.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	1.570s	1.083us	0	1	0.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	1.440s	1.047us	0	1	0.00
		rom_ctrl_csr_rw	1.440s	1.521us	0	1	0.00
		rom_ctrl_csr_aliasing	1.430s	1.087us	0	1	0.00
		rom_ctrl_same_csr_outstanding	1.410s	3.420us	0	1	0.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	1.440s	1.047us	0	1	0.00
		rom_ctrl_csr_rw	1.440s	1.521us	0	1	0.00
		rom_ctrl_csr_aliasing	1.430s	1.087us	0	1	0.00
		rom_ctrl_same_csr_outstanding	1.410s	3.420us	0	1	0.00
V2		TOTAL			0	6	0.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.390s	2.234us	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.520s	2.686us	0	1	0.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.530s	952.317ns	0	1	0.00
		rom_ctrl_tl_intg_err	1.440s	1.652us	0	1	0.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.530s	952.317ns	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.530s	952.317ns	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.390s	2.234us	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.390s	2.234us	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.390s	2.234us	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.390s	2.234us	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.390s	2.234us	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.530s	952.317ns	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.530s	952.317ns	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.440s	2.940us	0	1	0.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.440s	2.940us	0	1	0.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.440s	2.940us	0	1	0.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.440s	1.652us	0	1	0.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.390s	2.234us	0	1	0.00
		rom_ctrl_kmac_err_chk	1.350s	2.229us	0	1	0.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.390s	2.234us	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.390s	2.234us	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.390s	2.234us	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.520s	2.686us	0	1	0.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.530s	952.317ns	0	1	0.00
V2S		TOTAL			0	4	0.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.400s	1.128us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			0	19	0.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class! has 19 failures:

  • Test rom_ctrl_smoke has 1 failures.

    • 0.rom_ctrl_smoke.111367469130660086718793774752215277575363299267747757081579163923220686527695
      Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_smoke/latest/run.log

        UVM_FATAL @   2939973 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   2939973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_stress_all has 1 failures.

    • 0.rom_ctrl_stress_all.72851578770152110561342948245036680721399554399621445758937575220983546320312
      Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all/latest/run.log

        UVM_FATAL @   4572888 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   4572888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_max_throughput_chk has 1 failures.

    • 0.rom_ctrl_max_throughput_chk.52892195277868130263502168942050027476758577365967969466945390497262437871775
      Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest/run.log

        UVM_FATAL @   4253603 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   4253603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.20182418900246349035700750529611919181281969639382959688672192792399379145928
      Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_FATAL @   2233566 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   2233566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_kmac_err_chk has 1 failures.

    • 0.rom_ctrl_kmac_err_chk.28316516741981873070056585678898996068124765513400638353192698504996345843208
      Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest/run.log

        UVM_FATAL @   2228688 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   2228688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 14 more tests.