ROM_CTRL/64KB Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: 05d0058

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	2.030s	8.230us	0	1	0.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	2.060s	8.022us	0	1	0.00
V1	csr_rw	rom_ctrl_csr_rw	2.270s	5.181us	0	1	0.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	2.070s	1.663us	0	1	0.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	2.010s	6.351us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	2.070s	1.923us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	2.270s	5.181us	0	1	0.00
		rom_ctrl_csr_aliasing	2.010s	6.351us	0	1	0.00
V1	mem_walk	rom_ctrl_mem_walk	2.000s	1.335us	0	1	0.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	2.120s	1.984us	0	1	0.00
V1		TOTAL			0	8	0.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	2.030s	3.848us	0	1	0.00
V2	stress_all	rom_ctrl_stress_all	2.090s	3.194us	0	1	0.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	2.240s	10.467us	0	1	0.00
V2	alert_test	rom_ctrl_alert_test	2.050s	4.158us	0	1	0.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	1.970s	3.628us	0	1	0.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	1.970s	3.628us	0	1	0.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	2.060s	8.022us	0	1	0.00
		rom_ctrl_csr_rw	2.270s	5.181us	0	1	0.00
		rom_ctrl_csr_aliasing	2.010s	6.351us	0	1	0.00
		rom_ctrl_same_csr_outstanding	2.130s	9.438us	0	1	0.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	2.060s	8.022us	0	1	0.00
		rom_ctrl_csr_rw	2.270s	5.181us	0	1	0.00
		rom_ctrl_csr_aliasing	2.010s	6.351us	0	1	0.00
		rom_ctrl_same_csr_outstanding	2.130s	9.438us	0	1	0.00
V2		TOTAL			0	6	0.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.120s	2.674us	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	2.120s	1.480us	0	1	0.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.290s	2.468us	0	1	0.00
		rom_ctrl_tl_intg_err	2.180s	3.237us	0	1	0.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.290s	2.468us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	2.290s	2.468us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.120s	2.674us	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.120s	2.674us	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.120s	2.674us	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.120s	2.674us	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.120s	2.674us	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.290s	2.468us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.290s	2.468us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	2.030s	8.230us	0	1	0.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	2.030s	8.230us	0	1	0.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	2.030s	8.230us	0	1	0.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.180s	3.237us	0	1	0.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.120s	2.674us	0	1	0.00
		rom_ctrl_kmac_err_chk	2.240s	10.467us	0	1	0.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.120s	2.674us	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.120s	2.674us	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.120s	2.674us	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	2.120s	1.480us	0	1	0.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.290s	2.468us	0	1	0.00
V2S		TOTAL			0	4	0.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.040s	2.005us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			0	19	0.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class! has 19 failures:

  • Test rom_ctrl_smoke has 1 failures.

    • 0.rom_ctrl_smoke.70093359389539141255172813795127603509220240107502682368307432152497453891166
      Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_smoke/latest/run.log

        UVM_FATAL @   8230259 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   8230259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_stress_all has 1 failures.

    • 0.rom_ctrl_stress_all.71093813838671105747680085981087798334936295991990735494622274868844230936274
      Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all/latest/run.log

        UVM_FATAL @   3193854 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   3193854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_max_throughput_chk has 1 failures.

    • 0.rom_ctrl_max_throughput_chk.80490214377964907214549536840666288156604109322248069153846077903072159255036
      Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest/run.log

        UVM_FATAL @   3848206 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   3848206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.34976066461868255695964854194189287900783327798354192716245370828511621679385
      Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_FATAL @   2673792 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   2673792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_ctrl_kmac_err_chk has 1 failures.

    • 0.rom_ctrl_kmac_err_chk.106108815230044073792285993857772761878331260246694234101732412501590492658399
      Line 74, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest/run.log

        UVM_FATAL @  10467234 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rom_ctrl_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @  10467234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 14 more tests.