RV_DM/USE_JTAG_INTERFACE Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: 05d0058

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	0.750s	140.603us	0	1	0.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	0.620s	31.318us	0	1	0.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	0.630s	36.429us	0	1	0.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	0.650s	52.231us	0	1	0.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	0.580s	48.997us	0	1	0.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	0.630s	31.098us	0	1	0.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	0.700s	71.576us	0	1	0.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	0.650s	25.788us	0	1	0.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	0.760s	73.141us	0	1	0.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	0.630s	83.934us	0	1	0.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	0.600s	19.626us	0	1	0.00
V1	cmderr_exception	rv_dm_cmderr_exception	0.590s	60.562us	0	1	0.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	0.590s	38.252us	0	1	0.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.600s	49.403us	0	1	0.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	0.600s	64.311us	0	1	0.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.660s	25.518us	0	1	0.00
V1	halt_resume	rv_dm_halt_resume_whereto	0.690s	31.854us	0	1	0.00
V1	progbuf_busy	rv_dm_cmderr_busy	0.630s	83.934us	0	1	0.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.680s	74.153us	0	1	0.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	0.790s	96.846us	0	1	0.00
V1	progbuf_exception	rv_dm_cmderr_exception	0.590s	60.562us	0	1	0.00
V1	rom_read_access	rv_dm_rom_read_access	0.700s	70.645us	0	1	0.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	0.640s	62.195us	0	1	0.00
V1	csr_rw	rv_dm_csr_rw	0.670s	40.468us	0	1	0.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	0.660s	63.092us	0	1	0.00
V1	csr_aliasing	rv_dm_csr_aliasing	0.720s	84.242us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	0.660s	48.649us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	0.720s	84.242us	0	1	0.00
		rv_dm_csr_rw	0.670s	40.468us	0	1	0.00
V1	mem_walk	rv_dm_mem_walk	0.810s	116.007us	0	1	0.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.730s	79.505us	0	1	0.00
V1		TOTAL			0	27	0.00
V2	idcode	rv_dm_smoke	0.750s	140.603us	0	1	0.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	0.680s	93.779us	0	1	0.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.610s	23.072us	0	1	0.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.650s	29.993us	0	1	0.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	0.670s	49.679us	0	1	0.00
V2	sba	rv_dm_sba_tl_access	0.830s	120.340us	0	1	0.00
		rv_dm_delayed_resp_sba_tl_access	0.650s	16.226us	0	1	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	0.660s	32.151us	0	1	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	0.620s	65.820us	0	1	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	0.670s	15.956us	0	1	0.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	0.690s	87.244us	0	1	0.00
V2	ndmreset_req	rv_dm_ndmreset_req	0.620s	21.467us	0	1	0.00
V2	hart_unavail	rv_dm_hart_unavail	0.630s	32.762us	0	1	0.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	0.610s	15.552us	0	1	0.00
		rv_dm_tap_fsm_rand_reset	0.870s	150.544us	0	1	0.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.640s	16.081us	0	1	0.00
V2	stress_all	rv_dm_stress_all	0.680s	124.973us	0	1	0.00
V2	alert_test	rv_dm_alert_test	0.610s	26.857us	0	1	0.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	0.660s	139.557us	0	1	0.00
V2	tl_d_illegal_access	rv_dm_tl_errors	0.660s	139.557us	0	1	0.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	0.720s	84.242us	0	1	0.00
		rv_dm_csr_hw_reset	0.640s	62.195us	0	1	0.00
		rv_dm_csr_rw	0.670s	40.468us	0	1	0.00
		rv_dm_same_csr_outstanding	0.620s	53.182us	0	1	0.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	0.720s	84.242us	0	1	0.00
		rv_dm_csr_hw_reset	0.640s	62.195us	0	1	0.00
		rv_dm_csr_rw	0.670s	40.468us	0	1	0.00
		rv_dm_same_csr_outstanding	0.620s	53.182us	0	1	0.00
V2		TOTAL			0	19	0.00
V2S	tl_intg_err	rv_dm_sec_cm	0.820s	131.847us	0	1	0.00
		rv_dm_tl_intg_err	0.640s	23.308us	0	1	0.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	0.640s	23.308us	0	1	0.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	0.690s	87.244us	0	1	0.00
		rv_dm_debug_disabled	0.660s	135.982us	0	1	0.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	0.690s	87.244us	0	1	0.00
		rv_dm_debug_disabled	0.660s	135.982us	0	1	0.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	0.750s	140.603us	0	1	0.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	0.820s	135.154us	0	1	0.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.820s	125.538us	0	1	0.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.820s	125.538us	0	1	0.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	0.820s	135.154us	0	1	0.00
V2S		TOTAL			0	5	0.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	0.610s	50.287us	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	rv_dm_scanmode	0.650s	154.432us	0	1	0.00
		TOTAL			0	53	0.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class! has 53 failures:

  • Test rv_dm_csr_aliasing has 1 failures.

    • 0.rv_dm_csr_aliasing.10974510324523480865938614076191888056760816978999654135053773048846085296673
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest/run.log

        UVM_FATAL @  84241930 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @  84241930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_smoke has 1 failures.

    • 0.rv_dm_smoke.59243082399578703356132354524453781679075646944908520620225361271302021592863
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_smoke/latest/run.log

        UVM_FATAL @ 140602558 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @ 140602558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_tap_fsm has 1 failures.

    • 0.rv_dm_tap_fsm.111178375811197316974588077336421348846530156132860735354397733726726155807730
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log

        UVM_FATAL @  15552202 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @  15552202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_jtag_dtm_csr_hw_reset has 1 failures.

    • 0.rv_dm_jtag_dtm_csr_hw_reset.99963905162376452957538186181962636297849531407322769120045714927345730661924
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log

        UVM_FATAL @  31318251 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @  31318251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_jtag_dtm_csr_rw has 1 failures.

    • 0.rv_dm_jtag_dtm_csr_rw.108476621500891318079874399346820459428121221162241268639751448202060188328024
      Line 74, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest/run.log

        UVM_FATAL @  36428900 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_dm_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @  36428900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 48 more tests.