05d0058| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0.560s | 5.274us | 0 | 1 | 0.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.500s | 2.133us | 0 | 1 | 0.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.480s | 715.562ns | 0 | 1 | 0.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 0.490s | 1.458us | 0 | 1 | 0.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.480s | 1.286us | 0 | 1 | 0.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0.520s | 1.107us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.480s | 715.562ns | 0 | 1 | 0.00 |
| rv_timer_csr_aliasing | 0.480s | 1.286us | 0 | 1 | 0.00 | ||
| V1 | TOTAL | 0 | 6 | 0.00 | |||
| V2 | random_reset | rv_timer_random_reset | 0.520s | 4.326us | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 0.460s | 1.048us | 0 | 1 | 0.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 0.490s | 721.793ns | 0 | 1 | 0.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 0.490s | 721.793ns | 0 | 1 | 0.00 |
| V2 | stress | rv_timer_stress_all | 0.500s | 1.192us | 0 | 1 | 0.00 |
| V2 | alert_test | rv_timer_alert_test | 0.530s | 7.788us | 0 | 1 | 0.00 |
| V2 | intr_test | rv_timer_intr_test | 0.440s | 4.760us | 0 | 1 | 0.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 0.530s | 1.331us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 0.530s | 1.331us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.500s | 2.133us | 0 | 1 | 0.00 |
| rv_timer_csr_rw | 0.480s | 715.562ns | 0 | 1 | 0.00 | ||
| rv_timer_csr_aliasing | 0.480s | 1.286us | 0 | 1 | 0.00 | ||
| rv_timer_same_csr_outstanding | 0.540s | 987.800ns | 0 | 1 | 0.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.500s | 2.133us | 0 | 1 | 0.00 |
| rv_timer_csr_rw | 0.480s | 715.562ns | 0 | 1 | 0.00 | ||
| rv_timer_csr_aliasing | 0.480s | 1.286us | 0 | 1 | 0.00 | ||
| rv_timer_same_csr_outstanding | 0.540s | 987.800ns | 0 | 1 | 0.00 | ||
| V2 | TOTAL | 0 | 8 | 0.00 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.510s | 1.187us | 0 | 1 | 0.00 |
| rv_timer_tl_intg_err | 0.500s | 658.951ns | 0 | 1 | 0.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 0.500s | 658.951ns | 0 | 1 | 0.00 |
| V2S | TOTAL | 0 | 2 | 0.00 | |||
| V3 | min_value | rv_timer_min | 0.520s | 3.122us | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 0.490s | 5.349us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 0.480s | 6.567us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 0 | 19 | 0.00 |
UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [rv_timer_base_vseq] Need to override this when you extend from this class! has 19 failures:
Test rv_timer_random has 1 failures.
0.rv_timer_random.113028994897832785880921605943453546801803477675659349251737158191204184660483
Line 71, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random/latest/run.log
UVM_FATAL @ 5274348 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_timer_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 5274348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_min has 1 failures.
0.rv_timer_min.96495812917945078075274811759058724835648304468479212434558963800079698182839
Line 71, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 3121813 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_timer_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 3121813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_max has 1 failures.
0.rv_timer_max.108802655316672065223695123391833651000750096037837389950590460190564078346553
Line 71, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_FATAL @ 5349301 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_timer_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 5349301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_disabled has 1 failures.
0.rv_timer_disabled.77218745680655879199659672036466280242857179585759290501036469968103004367551
Line 71, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1048204 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_timer_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 1048204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_cfg_update_on_fly has 1 failures.
0.rv_timer_cfg_update_on_fly.87954360111267017561357975776915086263096492404054011615946183055495564119963
Line 71, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest/run.log
UVM_FATAL @ 721793 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [rv_timer_base_vseq] Need to override this when you extend from this class!
UVM_INFO @ 721793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more tests.