SPI_HOST Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: 05d0058

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	3.000s	1.169us	0	1	0.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	8.358us	0	1	0.00
V1	csr_rw	spi_host_csr_rw	3.000s	856.456ns	0	1	0.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	2.599us	0	1	0.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	2.235us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	914.346ns	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	856.456ns	0	1	0.00
		spi_host_csr_aliasing	2.000s	2.235us	0	1	0.00
V1	mem_walk	spi_host_mem_walk	3.000s	843.421ns	0	1	0.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	4.964us	0	1	0.00
V1		TOTAL			0	8	0.00
V2	performance	spi_host_performance	2.000s	1.775us	0	1	0.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	803.446ns	0	1	0.00
		spi_host_error_cmd	3.000s	5.039us	0	1	0.00
		spi_host_event	3.000s	1.446us	0	1	0.00
V2	clock_rate	spi_host_speed	3.000s	761.338ns	0	1	0.00
V2	speed	spi_host_speed	3.000s	761.338ns	0	1	0.00
V2	chip_select_timing	spi_host_speed	3.000s	761.338ns	0	1	0.00
V2	sw_reset	spi_host_sw_reset	3.000s	741.699ns	0	1	0.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	1.193us	0	1	0.00
V2	cpol_cpha	spi_host_speed	3.000s	761.338ns	0	1	0.00
V2	full_cycle	spi_host_speed	3.000s	761.338ns	0	1	0.00
V2	duplex	spi_host_smoke	3.000s	1.169us	0	1	0.00
V2	tx_rx_only	spi_host_smoke	3.000s	1.169us	0	1	0.00
V2	stress_all	spi_host_stress_all	3.000s	3.352us	0	1	0.00
V2	spien	spi_host_spien	2.000s	8.152us	0	1	0.00
V2	stall	spi_host_status_stall	3.000s	787.079ns	0	1	0.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	1.282us	0	1	0.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	803.446ns	0	1	0.00
V2	alert_test	spi_host_alert_test	3.000s	1.101us	0	1	0.00
V2	intr_test	spi_host_intr_test	3.000s	723.837ns	0	1	0.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	841.524ns	0	1	0.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	841.524ns	0	1	0.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	8.358us	0	1	0.00
		spi_host_csr_rw	3.000s	856.456ns	0	1	0.00
		spi_host_csr_aliasing	2.000s	2.235us	0	1	0.00
		spi_host_same_csr_outstanding	2.000s	1.046us	0	1	0.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	8.358us	0	1	0.00
		spi_host_csr_rw	3.000s	856.456ns	0	1	0.00
		spi_host_csr_aliasing	2.000s	2.235us	0	1	0.00
		spi_host_same_csr_outstanding	2.000s	1.046us	0	1	0.00
V2		TOTAL			0	15	0.00
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	2.686us	0	1	0.00
		spi_host_sec_cm	2.000s	3.445us	0	1	0.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	2.686us	0	1	0.00
V2S		TOTAL			0	2	0.00
	Unmapped tests	spi_host_upper_range_clkdiv	2.000s	1.098us	0	1	0.00
		TOTAL			0	26	0.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [spi_host_base_vseq] Need to override this when you extend from this class! has 26 failures:

  • Test spi_host_smoke has 1 failures.

    • 0.spi_host_smoke.48224882277655694314856235503573127810233973753590771285426433373816877845278
      Line 80, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_smoke/latest/run.log

        UVM_FATAL @   1168754 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [spi_host_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1168754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_speed has 1 failures.

    • 0.spi_host_speed.58323232775240547769336447383095898259464093667220013557255697124401449213697
      Line 80, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_speed/latest/run.log

        UVM_FATAL @    761338 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [spi_host_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @    761338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.19295959615071526595080099124272947557756920924379773982615919456608533509262
      Line 80, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @   1097608 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [spi_host_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1097608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_performance has 1 failures.

    • 0.spi_host_performance.1959078996151310908188119032682651142308505944478352075632521916116200028571
      Line 80, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_performance/latest/run.log

        UVM_FATAL @   1775207 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [spi_host_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1775207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_sw_reset has 1 failures.

    • 0.spi_host_sw_reset.73681461332662012474814576727917085526398345558359839409127355363409778813246
      Line 80, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_sw_reset/latest/run.log

        UVM_FATAL @    741699 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [spi_host_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @    741699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 21 more tests.