05d0058| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 0.540s | 0 | 1 | 0.00 | |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.540s | 0 | 1 | 0.00 | |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.500s | 0 | 1 | 0.00 | |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 0.510s | 0 | 1 | 0.00 | |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.500s | 0 | 1 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 0.480s | 0 | 1 | 0.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.500s | 0 | 1 | 0.00 | |
| sram_ctrl_csr_aliasing | 0.500s | 0 | 1 | 0.00 | |||
| V1 | mem_walk | sram_ctrl_mem_walk | 0.520s | 0 | 1 | 0.00 | |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 0.490s | 0 | 1 | 0.00 | |
| V1 | TOTAL | 0 | 8 | 0.00 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 0.500s | 0 | 1 | 0.00 | |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 0.520s | 0 | 1 | 0.00 | |
| V2 | bijection | sram_ctrl_bijection | 0.520s | 0 | 1 | 0.00 | |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 0.510s | 0 | 1 | 0.00 | |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 0.550s | 0 | 1 | 0.00 | |
| V2 | executable | sram_ctrl_executable | 0.490s | 0 | 1 | 0.00 | |
| V2 | partial_access | sram_ctrl_partial_access | 0.490s | 0 | 1 | 0.00 | |
| sram_ctrl_partial_access_b2b | 0.530s | 0 | 1 | 0.00 | |||
| V2 | max_throughput | sram_ctrl_max_throughput | 0.530s | 0 | 1 | 0.00 | |
| sram_ctrl_throughput_w_partial_write | 0.540s | 0 | 1 | 0.00 | |||
| sram_ctrl_throughput_w_readback | 0.490s | 0 | 1 | 0.00 | |||
| V2 | regwen | sram_ctrl_regwen | 0.530s | 0 | 1 | 0.00 | |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 0.530s | 0 | 1 | 0.00 | |
| V2 | stress_all | sram_ctrl_stress_all | 0.500s | 0 | 1 | 0.00 | |
| V2 | alert_test | sram_ctrl_alert_test | 0.500s | 0 | 1 | 0.00 | |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 0.520s | 0 | 1 | 0.00 | |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 0.520s | 0 | 1 | 0.00 | |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.540s | 0 | 1 | 0.00 | |
| sram_ctrl_csr_rw | 0.500s | 0 | 1 | 0.00 | |||
| sram_ctrl_csr_aliasing | 0.500s | 0 | 1 | 0.00 | |||
| sram_ctrl_same_csr_outstanding | 0.510s | 0 | 1 | 0.00 | |||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.540s | 0 | 1 | 0.00 | |
| sram_ctrl_csr_rw | 0.500s | 0 | 1 | 0.00 | |||
| sram_ctrl_csr_aliasing | 0.500s | 0 | 1 | 0.00 | |||
| sram_ctrl_same_csr_outstanding | 0.510s | 0 | 1 | 0.00 | |||
| V2 | TOTAL | 0 | 17 | 0.00 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 0.540s | 0 | 1 | 0.00 | |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 0.490s | 0 | 1 | 0.00 | |
| sram_ctrl_tl_intg_err | 0.510s | 0 | 1 | 0.00 | |||
| V2S | prim_count_check | sram_ctrl_sec_cm | 0.490s | 0 | 1 | 0.00 | |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 0.510s | 0 | 1 | 0.00 | |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 0.530s | 0 | 1 | 0.00 | |
| V2S | sec_cm_readback_config_regwen | sram_ctrl_regwen | 0.530s | 0 | 1 | 0.00 | |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.500s | 0 | 1 | 0.00 | |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 0.490s | 0 | 1 | 0.00 | |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 0.490s | 0 | 1 | 0.00 | |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 0.490s | 0 | 1 | 0.00 | |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 0.550s | 0 | 1 | 0.00 | |
| V2S | sec_cm_prim_ram_ctrl_mubi | sram_ctrl_mubi_enc_err | 0.480s | 0 | 1 | 0.00 | |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 0.540s | 0 | 1 | 0.00 | |
| V2S | sec_cm_mem_readback | sram_ctrl_readback_err | 0.500s | 0 | 1 | 0.00 | |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 0.540s | 0 | 1 | 0.00 | |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 0.540s | 0 | 1 | 0.00 | |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 0.490s | 0 | 1 | 0.00 | |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 0.490s | 0 | 1 | 0.00 | |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 0.550s | 0 | 1 | 0.00 | |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 0.490s | 0 | 1 | 0.00 | |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 0.490s | 0 | 1 | 0.00 | |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 0.540s | 0 | 1 | 0.00 | |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 0.490s | 0 | 1 | 0.00 | |
| V2S | TOTAL | 0 | 5 | 0.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 0.490s | 0 | 1 | 0.00 | |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 0 | 31 | 0.00 |
UVM_WARNING [BDTYP] Cannot create an object of type 'sram_ctrl_base_vseq' because it is not registered with the factory. has 31 failures:
Test sram_ctrl_smoke has 1 failures.
0.sram_ctrl_smoke.108801739310640045616429492707390797041958393674361709325759206411580329559034
Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'sram_ctrl_base_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
Test sram_ctrl_multiple_keys has 1 failures.
0.sram_ctrl_multiple_keys.6211011209431973394016933642538294300785925569185361196803201217348650202612
Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'sram_ctrl_base_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
Test sram_ctrl_bijection has 1 failures.
0.sram_ctrl_bijection.105672949884877568477115876087140046408451413319932257103642833416596223057605
Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_bijection/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'sram_ctrl_base_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
Test sram_ctrl_stress_pipeline has 1 failures.
0.sram_ctrl_stress_pipeline.32045396450152205589789200921892752568824393755321737636778589818701255577606
Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'sram_ctrl_base_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
Test sram_ctrl_partial_access has 1 failures.
0.sram_ctrl_partial_access.21852134341166117330786335508531749291785151135698147683574308551589164598128
Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_partial_access/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'sram_ctrl_base_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 26 more tests.