SYSRST_CTRL Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: 05d0058

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 3.840s 2.001ms 0 1 0.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 1.380s 2.001ms 0 1 0.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 1.230s 1.998ms 0 1 0.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.080s 2.002ms 0 1 0.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 1.560s 2.002ms 0 1 0.00
V1 csr_rw sysrst_ctrl_csr_rw 1.420s 2.002ms 0 1 0.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 4.260s 2.000ms 0 1 0.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 4.150s 2.001ms 0 1 0.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 4.410s 2.000ms 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 1.420s 2.002ms 0 1 0.00
sysrst_ctrl_csr_aliasing 4.150s 2.001ms 0 1 0.00
V1 TOTAL 0 9 0.00
V2 combo_detect sysrst_ctrl_combo_detect 1.590s 1.999ms 0 1 0.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 4.120s 2.000ms 0 1 0.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 1.420s 1.999ms 0 1 0.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 1.110s 2.001ms 0 1 0.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 1.330s 2.001ms 0 1 0.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.290s 1.999ms 0 1 0.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 0.820s 2.001ms 0 1 0.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.250s 2.002ms 0 1 0.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 3.820s 1.999ms 0 1 0.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 2.360s 2.000ms 0 1 0.00
V2 stress_all sysrst_ctrl_stress_all 3.860s 2.002ms 0 1 0.00
V2 alert_test sysrst_ctrl_alert_test 1.470s 2.000ms 0 1 0.00
V2 intr_test sysrst_ctrl_intr_test 1.530s 2.000ms 0 1 0.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 2.340s 1.999ms 0 1 0.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 2.340s 1.999ms 0 1 0.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 1.560s 2.002ms 0 1 0.00
sysrst_ctrl_csr_rw 1.420s 2.002ms 0 1 0.00
sysrst_ctrl_csr_aliasing 4.150s 2.001ms 0 1 0.00
sysrst_ctrl_same_csr_outstanding 2.230s 2.001ms 0 1 0.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 1.560s 2.002ms 0 1 0.00
sysrst_ctrl_csr_rw 1.420s 2.002ms 0 1 0.00
sysrst_ctrl_csr_aliasing 4.150s 2.001ms 0 1 0.00
sysrst_ctrl_same_csr_outstanding 2.230s 2.001ms 0 1 0.00
V2 TOTAL 0 15 0.00
V2S tl_intg_err sysrst_ctrl_sec_cm 1.420s 1.999ms 0 1 0.00
sysrst_ctrl_tl_intg_err 1.490s 2.002ms 0 1 0.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.490s 2.002ms 0 1 0.00
V2S TOTAL 0 2 0.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 1.530s 1.999ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 0 27 0.00

Failure Buckets