UART Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: 05d0058

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	0.560s	1.955us	0	1	0.00
V1	csr_hw_reset	uart_csr_hw_reset	0.510s	1.969us	0	1	0.00
V1	csr_rw	uart_csr_rw	0.520s	1.063us	0	1	0.00
V1	csr_bit_bash	uart_csr_bit_bash	0.500s	1.539us	0	1	0.00
V1	csr_aliasing	uart_csr_aliasing	0.540s	1.859us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.500s	3.049us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.520s	1.063us	0	1	0.00
		uart_csr_aliasing	0.540s	1.859us	0	1	0.00
V1		TOTAL			0	6	0.00
V2	base_random_seq	uart_tx_rx	0.600s	2.820us	0	1	0.00
V2	parity	uart_smoke	0.560s	1.955us	0	1	0.00
		uart_tx_rx	0.600s	2.820us	0	1	0.00
V2	parity_error	uart_intr	0.540s	17.039us	0	1	0.00
		uart_rx_parity_err	0.560s	1.136us	0	1	0.00
V2	watermark	uart_tx_rx	0.600s	2.820us	0	1	0.00
		uart_intr	0.540s	17.039us	0	1	0.00
V2	fifo_full	uart_fifo_full	0.530s	788.159ns	0	1	0.00
V2	fifo_overflow	uart_fifo_overflow	0.530s	2.804us	0	1	0.00
V2	fifo_reset	uart_fifo_reset	0.560s	788.887ns	0	1	0.00
V2	rx_frame_err	uart_intr	0.540s	17.039us	0	1	0.00
V2	rx_break_err	uart_intr	0.540s	17.039us	0	1	0.00
V2	rx_timeout	uart_intr	0.540s	17.039us	0	1	0.00
V2	perf	uart_perf	0.550s	3.339us	0	1	0.00
V2	sys_loopback	uart_loopback	0.560s	1.018us	0	1	0.00
V2	line_loopback	uart_loopback	0.560s	1.018us	0	1	0.00
V2	rx_noise_filter	uart_noise_filter	0.590s	8.085us	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	0.600s	5.651us	0	1	0.00
V2	tx_overide	uart_tx_ovrd	0.590s	680.513ns	0	1	0.00
V2	rx_oversample	uart_rx_oversample	0.530s	1.157us	0	1	0.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	0.530s	2.300us	0	1	0.00
V2	stress_all	uart_stress_all	0.520s	2.404us	0	1	0.00
V2	alert_test	uart_alert_test	0.510s	3.045us	0	1	0.00
V2	intr_test	uart_intr_test	0.550s	1.119us	0	1	0.00
V2	tl_d_oob_addr_access	uart_tl_errors	0.520s	7.727us	0	1	0.00
V2	tl_d_illegal_access	uart_tl_errors	0.520s	7.727us	0	1	0.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.510s	1.969us	0	1	0.00
		uart_csr_rw	0.520s	1.063us	0	1	0.00
		uart_csr_aliasing	0.540s	1.859us	0	1	0.00
		uart_same_csr_outstanding	0.470s	991.150ns	0	1	0.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.510s	1.969us	0	1	0.00
		uart_csr_rw	0.520s	1.063us	0	1	0.00
		uart_csr_aliasing	0.540s	1.859us	0	1	0.00
		uart_same_csr_outstanding	0.470s	991.150ns	0	1	0.00
V2		TOTAL			0	18	0.00
V2S	tl_intg_err	uart_sec_cm	0.500s	782.478ns	0	1	0.00
		uart_tl_intg_err	0.490s	3.239us	0	1	0.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.490s	3.239us	0	1	0.00
V2S		TOTAL			0	2	0.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	0.550s	843.506ns	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			0	27	0.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:123) virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class! has 27 failures:

  • Test uart_smoke has 1 failures.

    • 0.uart_smoke.6762038604170380511680750701229240651278294294971673427787303301955595111212
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_smoke/latest/run.log

        UVM_FATAL @   1954522 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   1954522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test uart_tx_rx has 1 failures.

    • 0.uart_tx_rx.51357864831021340985571758308686454835741786819436312678537926310431673542437
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_tx_rx/latest/run.log

        UVM_FATAL @   2819552 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   2819552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test uart_fifo_full has 1 failures.

    • 0.uart_fifo_full.96611586070612239699722817000551959149670399276274717750854932954077859257417
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_fifo_full/latest/run.log

        UVM_FATAL @    788159 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @    788159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test uart_fifo_overflow has 1 failures.

    • 0.uart_fifo_overflow.114290713827687878135984751582311265426410823247800466068039689383557306636748
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_fifo_overflow/latest/run.log

        UVM_FATAL @   2804112 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @   2804112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test uart_fifo_reset has 1 failures.

    • 0.uart_fifo_reset.13151447542814982224412447189787186305162141961310265686409068474412810316820
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_fifo_reset/latest/run.log

        UVM_FATAL @    788887 ps: (cip_base_vseq.sv:123) uvm_test_top.env.virtual_sequencer [uart_base_vseq] Need to override this when you extend from this class!
        UVM_INFO @    788887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 22 more tests.