CHIP Simulation Results

Thursday August 28 2025 14:12:23 UTC

GitHub Revision: `05d0058`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.409m	2.664ms	1	1	100.00
		chip_sw_example_rom	1.033m	2.605ms	1	1	100.00
		chip_sw_example_manufacturer	1.845m	2.590ms	1	1	100.00
		chip_sw_example_concurrency	1.452m	2.045ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	15.980s	10.340us	0	1	0.00
V1	csr_rw	chip_csr_rw	15.690s	10.260us	0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	15.910s	10.260us	0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	16.280s	10.360us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	15.550s	10.260us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	16.280s	10.360us	0	1	0.00
		chip_csr_rw	15.690s	10.260us	0	1	0.00
V1	xbar_smoke	xbar_smoke	15.720s	11.494us	0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	12.570m	12.019ms	0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	12.570m	12.019ms	0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	12.570m	12.019ms	0	1	0.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	28.721m	12.027ms	0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	28.721m	12.027ms	0	1	0.00
		chip_sw_uart_tx_rx_idx1	27.257m	12.027ms	0	1	0.00
		chip_sw_uart_tx_rx_idx2	27.404m	12.019ms	0	1	0.00
		chip_sw_uart_tx_rx_idx3	26.804m	12.019ms	0	1	0.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate			0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq			0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed			0	1	0.00
V1		TOTAL			4	18	22.22
V2	chip_pin_mux	chip_padctrl_attributes	15.680s	10.400us	0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	15.680s	10.400us	0	1	0.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.088m	12.027ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.264m	12.019ms	0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	4.131m	12.018ms	0	1	0.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.438m	2.581ms	1	1	100.00
		chip_tap_straps_testunlock0	1.387m	2.754ms	1	1	100.00
		chip_tap_straps_rma	1.220m	2.505ms	1	1	100.00
		chip_tap_straps_prod	1.232m	2.292ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.386m	3.415ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	10.867m	8.353ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.815m	2.829ms	0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.815m	2.829ms	0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.219m	6.618ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	14.329m	8.075ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.573m	4.601ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.816m	6.045ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.086m	18.749ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.594m	3.116ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.756m	5.150ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.836m	3.004ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.892m	11.972ms	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	2.016m	2.303ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.578m	5.661ms	0	1	0.00
		chip_sw_clkmgr_jitter	1.982m	2.358ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	26.938m	12.027ms	0	1	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	8.916m	8.956ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.341m	4.968ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	42.320m	40.018ms	0	1	0.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.341m	4.968ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.092m	3.041ms	1	1	100.00
		chip_sw_aes_smoketest	2.104m	2.736ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.075m	3.232ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.792m	2.700ms	1	1	100.00
		chip_sw_csrng_smoketest	1.977m	2.348ms	1	1	100.00
		chip_sw_entropy_src_smoketest	14.815m	7.334ms	1	1	100.00
		chip_sw_gpio_smoketest	2.681m	3.399ms	1	1	100.00
		chip_sw_hmac_smoketest	3.289m	3.224ms	1	1	100.00
		chip_sw_kmac_smoketest	2.783m	2.785ms	1	1	100.00
		chip_sw_otbn_smoketest	12.728m	7.238ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.076m	6.382ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.840m	5.927ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.737m	2.688ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.511m	2.949ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.224m	2.709ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.084m	3.611ms	1	1	100.00
		chip_sw_uart_smoketest	2.555m	3.177ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.972m	2.764ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	3.577m	3.977ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.203h	70.104ms	0	1	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke	41.751m	15.437ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	1.070h	200.018ms	0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	6.328m	4.491ms	1	1	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.132m	3.864ms	1	1	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.001m	3.418ms	0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.267m	2.898ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	15.640s	10.260us	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	15.640s	10.260us	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	16.280s	10.360us	0	1	0.00
		chip_same_csr_outstanding	16.420s	10.200us	0	1	0.00
		chip_csr_hw_reset	15.980s	10.340us	0	1	0.00
		chip_csr_rw	15.690s	10.260us	0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	16.280s	10.360us	0	1	0.00
		chip_same_csr_outstanding	16.420s	10.200us	0	1	0.00
		chip_csr_hw_reset	15.980s	10.340us	0	1	0.00
		chip_csr_rw	15.690s	10.260us	0	1	0.00
V2	xbar_base_random_sequence	xbar_random	16.030s	12.381us	0	1	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays	15.770s	10.948us	0	1	0.00
		xbar_smoke_large_delays	16.030s	11.272us	0	1	0.00
		xbar_smoke_slow_rsp	15.800s	11.397us	0	1	0.00
		xbar_random_zero_delays	16.240s	11.178us	0	1	0.00
		xbar_random_large_delays	16.140s	10.930us	0	1	0.00
		xbar_random_slow_rsp	15.640s	11.012us	0	1	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr	16.180s	12.138us	0	1	0.00
		xbar_error_and_unmapped_addr	15.560s	12.113us	0	1	0.00
V2	xbar_error_cases	xbar_error_random	16.130s	11.749us	0	1	0.00
		xbar_error_and_unmapped_addr	15.560s	12.113us	0	1	0.00
V2	xbar_all_access_same_device	xbar_access_same_device	16.110s	11.430us	0	1	0.00
		xbar_access_same_device_slow_rsp	16.500s	12.037us	0	1	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	15.490s	11.515us	0	1	0.00
V2	xbar_stress_all	xbar_stress_all	15.850s	11.734us	0	1	0.00
		xbar_stress_all_with_error	16.070s	11.140us	0	1	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	15.650s	11.100us	0	1	0.00
		xbar_stress_all_with_reset_error	15.710s	11.376us	0	1	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.751m	15.437ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	23.805m	20.019ms	0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.314h	40.018ms	0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	33.930m	12.244ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	43.653m	15.465ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	43.514m	15.995ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	42.284m	15.951ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	41.635m	14.535ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	22.070s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	16.990s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	19.830s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.020s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.360s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.160s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	16.350s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	18.180s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.200s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.190s	10.140us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.040s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.180s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	16.720s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.700s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	16.400s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.110s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.720s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.590s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.700s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	15.590s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.820s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.040s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.060s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.830s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.750s	10.400us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	35.909m	17.952ms	1	1	100.00
		rom_e2e_asm_init_dev	42.869m	15.688ms	1	1	100.00
		rom_e2e_asm_init_prod	41.285m	15.861ms	1	1	100.00
		rom_e2e_asm_init_prod_end	43.375m	17.883ms	1	1	100.00
		rom_e2e_asm_init_rma	39.877m	16.322ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	41.450m	14.962ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	41.747m	17.354ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	38.955m	15.995ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	41.317m	18.404ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2.438m	2.565ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2.438m	2.565ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	1.764m	2.801ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.594m	3.116ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.513m	2.883ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.431m	3.053ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	13.656m	8.485ms	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.355m	2.924ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.354m	5.570ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	2.831m	3.470ms	0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.212m	5.137ms	1	1	100.00
		chip_plic_all_irqs_10	3.102m	3.006ms	1	1	100.00
		chip_plic_all_irqs_20	5.755m	4.846ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.564m	3.220ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.771m	13.640ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	2.938m	3.367ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.102m	3.353ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	7.595m	8.649ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.569m	7.645ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.385m	7.251ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.768m	7.567ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.224h	256.323ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.125m	4.213ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.076m	6.382ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.125m	4.213ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.914m	8.897ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.914m	8.897ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.525m	6.352ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.307m	5.264ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.339m	5.848ms	1	1	100.00
		chip_sw_aes_idle	2.431m	3.053ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.524m	2.831ms	1	1	100.00
		chip_sw_kmac_idle	1.595m	2.261ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.288m	3.774ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.574m	3.809ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.505m	4.349ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.741m	3.694ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.396m	9.975ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.345m	3.891ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.145m	5.099ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.924m	4.158ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.334m	4.076ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.270m	3.675ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.695m	4.465ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.219m	6.618ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	2.238m	2.750ms	0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.924m	4.158ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.334m	4.076ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.573m	4.601ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.816m	6.045ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.086m	18.749ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.594m	3.116ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.756m	5.150ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.836m	3.004ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.892m	11.972ms	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	2.016m	2.303ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.578m	5.661ms	0	1	0.00
		chip_sw_clkmgr_jitter	1.982m	2.358ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.174m	2.865ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.142m	4.499ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	8.918m	7.347ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	51.947m	24.927ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.962m	3.013ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.601m	3.669ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	14.123m	10.002ms	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.701m	3.042ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.222m	6.764ms	0	1	0.00
		chip_sw_flash_init_reduced_freq	1.212m	2.238ms	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.782h	124.535ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.219m	6.618ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.109m	4.743ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.815m	3.539ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	2.831m	3.470ms	0	1	0.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	16.569m	7.645ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.694m	6.428ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.821m	4.137ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	15.144m	15.027ms	0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.991m	2.858ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	28.691m	11.193ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.405m	2.351ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.695m	5.828ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.405m	2.351ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.694m	6.428ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.809m	2.792ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	1.311m	2.770ms	0	1	0.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.648m	5.018ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.816m	6.045ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	4.569m	4.491ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.573m	4.601ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.291m	2.623ms	0	1	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	1.311m	2.770ms	0	1	0.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.226m	2.897ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	18.254m	9.864ms	0	1	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	12.203m	12.019ms	0	1	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.291m	2.623ms	0	1	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	12.203m	12.019ms	0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	12.203m	12.019ms	0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	12.203m	12.019ms	0	1	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	12.203m	12.019ms	0	1	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	2.831m	3.470ms	0	1	0.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	16.200s	10.400us	0	1	0.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.263m	4.400ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	3.954m	3.157ms	0	1	0.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	3.954m	3.157ms	0	1	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.735m	2.892ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.836m	3.004ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.524m	2.831ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.755m	2.601ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	3.879m	3.679ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	20.472m	12.019ms	0	1	0.00
		chip_sw_i2c_host_tx_rx_idx1	17.244m	12.027ms	0	1	0.00
		chip_sw_i2c_host_tx_rx_idx2	19.276m	12.019ms	0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	16.898m	12.018ms	0	1	0.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	18.254m	9.864ms	0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en	24.892m	11.972ms	0	1	0.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	12.136m	7.025ms	0	1	0.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	13.656m	8.485ms	0	1	0.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	39.282m	15.507ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.497m	2.815ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.637m	3.409ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.016m	2.303ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	18.254m	9.864ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	2.400m	3.256ms	0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.000m	3.043ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	21.942m	9.884ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.595m	2.261ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.354m	5.570ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.438m	2.581ms	1	1	100.00
		chip_tap_straps_rma	1.220m	2.505ms	1	1	100.00
		chip_tap_straps_prod	1.232m	2.292ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.567m	2.626ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	2.400m	3.256ms	0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	2.400m	3.256ms	0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	2.400m	3.256ms	0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	27.518m	12.996ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	12.203m	12.019ms	0	1	0.00
		chip_sw_flash_rma_unlocked	1.291m	2.623ms	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.172m	3.183ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.162m	7.591ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.829m	7.519ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.583m	5.425ms	1	1	100.00
		chip_sw_lc_ctrl_transition	2.400m	3.256ms	0	1	0.00
		chip_sw_keymgr_key_derivation	18.254m	9.864ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	2.488m	2.529ms	0	1	0.00
		chip_sw_sram_ctrl_execution_main	10.210m	12.027ms	0	1	0.00
		chip_prim_tl_access	16.200s	10.400us	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	2.238m	2.750ms	0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.345m	3.891ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.145m	5.099ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.924m	4.158ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.334m	4.076ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.270m	3.675ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.695m	4.465ms	1	1	100.00
		chip_tap_straps_dev	1.438m	2.581ms	1	1	100.00
		chip_tap_straps_rma	1.220m	2.505ms	1	1	100.00
		chip_tap_straps_prod	1.232m	2.292ms	1	1	100.00
		chip_rv_dm_lc_disabled	16.170s	10.220us	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.531m	2.818ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.115m	2.496ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.558m	2.418ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.162m	2.921ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	5.668m	12.019ms	0	1	0.00
		chip_rv_dm_lc_disabled	16.170s	10.220us	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.721h	200.018ms	0	1	0.00
		chip_sw_lc_walkthrough_prod	1.577h	200.027ms	0	1	0.00
		chip_sw_lc_walkthrough_prodend	4.638m	12.027ms	0	1	0.00
		chip_sw_lc_walkthrough_rma	1.257h	200.027ms	0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	5.668m	12.019ms	0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	5.003m	12.019ms	0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	4.722m	12.018ms	0	1	0.00
		rom_volatile_raw_unlock	1.414h	200.019ms	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.291m	16.946ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.086m	18.749ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.339m	5.848ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.339m	5.848ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.339m	5.848ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.373m	3.619ms	0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	2.400m	3.256ms	0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	1.311m	2.770ms	0	1	0.00
		chip_sw_otbn_mem_scramble	4.373m	3.619ms	0	1	0.00
		chip_sw_keymgr_key_derivation	18.254m	9.864ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.223m	5.364ms	0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	2.029m	3.125ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	1.311m	2.770ms	0	1	0.00
		chip_sw_otbn_mem_scramble	4.373m	3.619ms	0	1	0.00
		chip_sw_keymgr_key_derivation	18.254m	9.864ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.223m	5.364ms	0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	2.029m	3.125ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	2.400m	3.256ms	0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.387m	12.027ms	0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.567m	2.626ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.172m	3.183ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.162m	7.591ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.829m	7.519ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.583m	5.425ms	1	1	100.00
		chip_sw_lc_ctrl_transition	2.400m	3.256ms	0	1	0.00
		chip_prim_tl_access	16.200s	10.400us	0	1	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	16.200s	10.400us	0	1	0.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.351m	8.578ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	2.382m	3.490ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	2.078m	2.923ms	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	2.314m	3.073ms	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	2.249m	2.824ms	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	2.045m	2.411ms	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1.977m	3.252ms	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	2.462m	3.276ms	0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	7.914m	8.897ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	2.328m	3.191ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.581m	5.410ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	2.382m	3.490ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	11.817m	12.027ms	0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	4.159m	24.027ms	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.577m	12.019ms	0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	2.867m	12.027ms	0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	2.547m	2.610ms	0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	1.851m	2.481ms	0	1	0.00
		chip_sw_pwrmgr_all_reset_reqs	1.833m	3.272ms	0	1	0.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	2.233m	2.741ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	1.799m	2.276ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	2.831m	3.470ms	0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	2.488m	2.529ms	0	1	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	2.488m	2.529ms	0	1	0.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	1.833m	3.272ms	0	1	0.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	2.547m	2.610ms	0	1	0.00
		chip_sw_pwrmgr_wdog_reset	4.581m	5.410ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.076m	6.382ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	12.065m	12.018ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.798m	4.229ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.045m	4.586ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.771m	13.640ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.167m	2.697ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	2.831m	3.470ms	0	1	0.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.385m	7.251ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.606m	4.830ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.679m	4.247ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.441m	2.546ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.029m	3.125ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.798m	4.229ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.798m	4.229ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	16.800s	10.140us	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	17.410s	10.260us	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	12.065m	12.018ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	24.199m	12.019ms	0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	25.861m	12.027ms	0	1	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	1.220m	2.505ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	16.170s	10.220us	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.212m	5.137ms	1	1	100.00
		chip_plic_all_irqs_10	3.102m	3.006ms	1	1	100.00
		chip_plic_all_irqs_20	5.755m	4.846ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.465m	2.513ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	1.757m	3.067ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.751m	15.437ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.756m	12.019ms	0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	11.029m	12.027ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	12.952m	12.018ms	0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.911m	3.627ms	0	1	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.223m	5.364ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.578m	5.661ms	0	1	0.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.210m	7.509ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.631m	6.447ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.210m	12.027ms	0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	2.831m	3.470ms	0	1	0.00
		chip_sw_data_integrity_escalation	1.815m	2.829ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	1.851m	2.481ms	0	1	0.00
		chip_sw_sysrst_ctrl_reset	2.790m	2.867ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.624m	3.032ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.657m	3.069ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	2.460m	2.879ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	2.790m	2.867ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	2.790m	2.867ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.541m	2.217ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.541m	2.217ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	1.401m	2.270ms	0	1	0.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2.438m	2.565ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.313m	2.495ms	0	1	0.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.941m	2.685ms	0	1	0.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	1.867m	2.774ms	0	1	0.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	2.448m	2.991ms	0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	2.021m	3.226ms	0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.889m	2.683ms	0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	2.141m	2.404ms	0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.336m	3.186ms	0	1	0.00
V2		TOTAL			138	275	50.18
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.039m	2.708ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.124m	2.616ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.513h	71.512ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus			0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	7.854m	12.019ms	0	1	0.00
		rom_e2e_jtag_debug_dev	6.194m	12.019ms	0	1	0.00
		rom_e2e_jtag_debug_rma	6.045m	12.019ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	22.274m	40.018ms	0	1	0.00
		rom_e2e_jtag_inject_dev	16.083m	40.027ms	0	1	0.00
		rom_e2e_jtag_inject_rma	15.818m	40.027ms	0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	14.701s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.485m	4.708ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.367m	3.084ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	6.574m	3.741ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	17.587m	9.067ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.216m	2.446ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.834m	4.849ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.306m	2.853ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	3.995m	3.435ms	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.475m	18.019ms	0	1	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.459m	4.479ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	1.833m	3.272ms	0	1	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	7.854m	12.019ms	0	1	0.00
		rom_e2e_jtag_debug_dev	6.194m	12.019ms	0	1	0.00
		rom_e2e_jtag_debug_rma	6.045m	12.019ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.575m	4.775ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	2.831m	3.470ms	0	1	0.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.428h	38.537ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.428h	38.537ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	1.830m	2.342ms	0	1	0.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	28.721m	12.027ms	0	1	0.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	2.897m	3.338ms	0	1	0.00
V3		TOTAL			11	23	47.83
	Unmapped tests	chip_sival_flash_info_access	2.417m	2.819ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	3.307m	3.436ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.740m	2.704ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.058m	2.369ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.309m	4.459ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.360s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.923m	3.033ms	1	1	100.00
		TOTAL			160	325	49.23

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom]] file .*.scr.vmem could not be opened for r mode has 30 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.7590912847912188408194006010858226097747391401156172725746561199864610665419
    Line 216, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.40468303713051127429412065101847534050351408461407432594371901044205381536152
    Line 216, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.8593605024637875287996348043423117633864013584549283273322021354318054935305
    Line 216, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.15596248812188112191921596004649082321964968259857289672356907586715412726037
    Line 216, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_prim_tl_access has 1 failures.
  - 0.chip_prim_tl_access.90613510936032420563043314635130130737485944937813302476779572502779323449511
    Line 216, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom]] file .39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 25 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 28 failures:

Test chip_sw_sleep_pin_mio_dio_val has 1 failures.

0.chip_sw_sleep_pin_mio_dio_val.31273996676376529400841182182549673552821569319311634027381351381929504603860
Line 591, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log

  UVM_ERROR @ 12026.811198 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.811198 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.10848650321769293568670214484713598928694291525657097552222329697685372877937
Line 506, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  UVM_ERROR @ 12018.613383 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.613383 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.94537135762909471587407299787416651271878713861921806876176410753129010710040
Line 564, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  UVM_ERROR @ 12018.495836 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.495836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.47519866164508481944201583429608771952273904879162276871348666119623606692007
Line 537, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  UVM_ERROR @ 12026.992792 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.992792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_uart_tx_rx_idx1 has 1 failures.

0.chip_sw_uart_tx_rx_idx1.4891196520528928765793816943358451403184016812452682943541495669200308774504
Line 554, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_idx1/latest/run.log

  UVM_ERROR @ 12026.998062 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.998062 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 23 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 17 failures:

Test chip_sw_lc_walkthrough_dev has 1 failures.

0.chip_sw_lc_walkthrough_dev.51974579492472493659402906441889644977239771767606250530843477901762428140453
Line 423, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log

  UVM_ERROR @ 200018.386969 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns

  UVM_INFO @ 200018.386969 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_walkthrough_prod has 1 failures.

0.chip_sw_lc_walkthrough_prod.50383032755594929899447175339019741897130055107173488913337480647374988673557
Line 417, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log

  UVM_ERROR @ 200026.927429 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns

  UVM_INFO @ 200026.927429 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_walkthrough_prodend has 1 failures.

0.chip_sw_lc_walkthrough_prodend.87875456170241406395716540199920054557886390232424229392610239778541434355535
Line 420, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest/run.log

  UVM_ERROR @ 12026.860393 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.860393 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_volatile_raw_unlock has 1 failures.

0.chip_sw_lc_ctrl_volatile_raw_unlock.40626433261903240507901749418077757493732703521632692290571357140337348103579
Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log

  UVM_ERROR @ 12018.545589 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.545589 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz has 1 failures.
- 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.79893432543890606496089108847057320695172182804997197538540937443337509948515
  Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log
```
  UVM_ERROR @ 12018.439115 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.439115 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
... and 12 more tests.

Offending '(!$isunknown(cio_key0_out_o))' has 12 failures:
- Test chip_sw_pwrmgr_sysrst_ctrl_reset has 1 failures.
  - 0.chip_sw_pwrmgr_sysrst_ctrl_reset.74027851535070497972131199194905904792896658609992783017337533970262332682347
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest/run.log
```
      Offending '(!$isunknown(cio_key0_out_o))'
  UVM_ERROR @ 2480.759456 us: (sysrst_ctrl.sv:369) [ASSERT FAILED] Key0OKnown_A
  UVM_INFO @ 2480.759456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_all_reset_reqs.71771719450199619783468748315201587791977638033913680740928280888682318860567
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_all_reset_reqs/latest/run.log
```
      Offending '(!$isunknown(cio_key0_out_o))'
  UVM_ERROR @ 3272.156712 us: (sysrst_ctrl.sv:369) [ASSERT FAILED] Key0OKnown_A
  UVM_INFO @ 3272.156712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.22518067042008769821660171069141442764002488979730879346531406765192856157862
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(!$isunknown(cio_key0_out_o))'
  UVM_ERROR @ 2610.222768 us: (sysrst_ctrl.sv:369) [ASSERT FAILED] Key0OKnown_A
  UVM_INFO @ 2610.222768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.28118405507419513443413809787701719790273857697495410727340529235159478365285
    Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(!$isunknown(cio_key0_out_o))'
  UVM_ERROR @ 3276.383656 us: (sysrst_ctrl.sv:369) [ASSERT FAILED] Key0OKnown_A
  UVM_INFO @ 3276.383656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_normal_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.99963625096915666642699265419478707267978702252150966240419810395426597784177
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log
```
      Offending '(!$isunknown(cio_key0_out_o))'
  UVM_ERROR @ 3191.456104 us: (sysrst_ctrl.sv:369) [ASSERT FAILED] Key0OKnown_A
  UVM_INFO @ 3191.456104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 7 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.61600514231248362059452131535464129755112621128994012563190522205903278170041
    Line 498, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.58804964835908260411498818972251251224836187140028302497997488860304481094030
    Line 516, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.74294705492037737167751620286444030245179802072818192241826287031232736682079
    Line 515, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.87535404250827214181968294141969785709338469702887713020064519003183941039074
    Line 585, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.74654674292871441398171429586283714244717390129607718972430203870625761038727
    Line 572, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 10 failures:

Test chip_sw_usbdev_vbus has 1 failures.

0.chip_sw_usbdev_vbus.113751805086187388246305391836044720290343551299316249495306629993176234413484
Line 587, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_vbus/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 2494.887596 us: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_M
  UVM_INFO @ 2494.887596 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_usbdev_dpi has 1 failures.

0.chip_sw_usbdev_dpi.17374836712312678259233482703531872429185874981381029491775799078335469607946
Line 588, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_dpi/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 2404.115666 us: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_M
  UVM_INFO @ 2404.115666 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_usbdev_pullup has 1 failures.

0.chip_sw_usbdev_pullup.93090904916547151845241231444769327091217105129528443112568327897987420479002
Line 569, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_pullup/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 2685.372689 us: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_M
  UVM_INFO @ 2685.372689 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_usbdev_aon_pullup has 1 failures.

0.chip_sw_usbdev_aon_pullup.15244367666367327308821314001779810502231017599433707885998109737452453091483
Line 525, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_aon_pullup/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 2774.228267 us: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_M
  UVM_INFO @ 2774.228267 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_usbdev_setuprx has 1 failures.

0.chip_sw_usbdev_setuprx.85171001696736623054302655438523968535148583288692133983524068687170008551137
Line 561, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_setuprx/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 2991.289131 us: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_M
  UVM_INFO @ 2991.289131 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more tests.

UVM_ERROR @ * us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== has 5 failures:
- Test chip_sw_exit_test_unlocked_bootstrap has 1 failures.
  - 0.chip_sw_exit_test_unlocked_bootstrap.93714001994358883837941718439012771848442729849244640926997103970398789491822
    Line 491, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  UVM_ERROR @ 3418.147528 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 3418.147528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_spi_host_tx_rx has 1 failures.
  - 0.chip_sw_spi_host_tx_rx.2894647739124541640386855231182317647352080996806294935768014607128485437693
    Line 616, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_host_tx_rx/latest/run.log
```
  UVM_ERROR @ 3626.874792 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 3626.874792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_sideload_kmac has 1 failures.
  - 0.chip_sw_keymgr_sideload_kmac.7599709470460663383715588228224018246023973760040072439879119272082888963534
    Line 428, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_kmac/latest/run.log
```
  UVM_ERROR @ 7025.425332 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 7025.425332 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_sideload_aes has 1 failures.
  - 0.chip_sw_keymgr_sideload_aes.61115599099559786524413683716341274676294991181109764793720538195434333771580
    Line 425, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_aes/latest/run.log
```
  UVM_ERROR @ 8484.680505 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 8484.680505 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_rom_ctrl_integrity_check has 1 failures.
  - 0.chip_sw_rom_ctrl_integrity_check.52204852113674961880917338382173793605824947470331439113145062394495446846646
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rom_ctrl_integrity_check/latest/run.log
```
  UVM_ERROR @ 2529.212384 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 2529.212384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.21219878225842985263419815295852996326120235472899453230647808233553903102271
    Line 526, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.110576119245193364071084094157558180617906975207784987316875430447500884843317
    Line 515, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.95933271230837959238289347051991490604901713206672245675946191586636194377453
    Line 501, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.13776377406173758527998169601121366371285619361151333574629231125964067009910
    Line 483, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.64097738778965153106364854281624752246062853117972903005862989826207201554365
    Line 511, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:736)] CHECK-fail: Alert handler NMI state not expected: has 4 failures:

Test chip_sw_all_escalation_resets has 1 failures.

0.chip_sw_all_escalation_resets.32609468777884071905754581633982373391961701164064493736159925076382236130320
Line 565, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

  UVM_ERROR @ 3470.232840 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:736)] CHECK-fail: Alert handler NMI state not expected:
      alert_enable:1
      alert_raised:0
  UVM_INFO @ 3470.232840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.

0.chip_sw_rstmgr_rst_cnsty_escalation.7847265011939979650574331873920872900453835494924454027173027605495920693861
Line 499, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

  UVM_ERROR @ 3435.521191 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:736)] CHECK-fail: Alert handler NMI state not expected:
      alert_enable:1
      alert_raised:0
  UVM_INFO @ 3435.521191 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_otp_ctrl_escalation has 1 failures.

0.chip_sw_otp_ctrl_escalation.106129032675902213886257116226039044508645778680701015944581112507155045848951
Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log

  UVM_ERROR @ 3435.136604 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:736)] CHECK-fail: Alert handler NMI state not expected:
      alert_enable:1
      alert_raised:0
  UVM_INFO @ 3435.136604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_flash_crash_alert has 1 failures.

0.chip_sw_flash_crash_alert.70378289450555746044895185708472781070934566408656440175758671918923508404626
Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_crash_alert/latest/run.log

  UVM_ERROR @ 3156.570778 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:736)] CHECK-fail: Alert handler NMI state not expected:
      alert_enable:1
      alert_raised:0
  UVM_INFO @ 3156.570778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job timed out after * minutes has 4 failures:
- Test chip_sw_uart_rand_baudrate has 1 failures.
  - 0.chip_sw_uart_rand_baudrate.30795699156186242373254772882053750743390246596422336113626441584687127177729
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest/run.log
```
  Job timed out after 120 minutes
```
- Test chip_sw_uart_tx_rx_alt_clk_freq has 1 failures.
  - 0.chip_sw_uart_tx_rx_alt_clk_freq.83163014982298057549043071636049795882409188080053901221469925405281627869394
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log
```
  Job timed out after 120 minutes
```
- Test chip_sw_uart_tx_rx_alt_clk_freq_low_speed has 1 failures.
  - 0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.72964193180135991246566045780990001947943479567781544915362682225070978248402
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.110254690215741724422736171841328589732489982159106545145540297581831141139283
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job timed out after 300 minutes
```
Offending '(!$isunknown(cio_pwrb_out_o))' has 4 failures:
- Test chip_sw_sysrst_ctrl_ulp_z3_wakeup has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.41733224625104524612615775214086392982463653399681887493732486006543273090247
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest/run.log
```
      Offending '(!$isunknown(cio_pwrb_out_o))'
  UVM_ERROR @ 2270.063396 us: (sysrst_ctrl.sv:368) [ASSERT FAILED] PwrbOKnown_A
  UVM_INFO @ 2270.063396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 1 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3409467769914258907895721796571360347642993507830629239306973279703610092068
    Line 392, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
      Offending '(!$isunknown(cio_pwrb_out_o))'
  UVM_ERROR @ 3073.407848 us: (sysrst_ctrl.sv:368) [ASSERT FAILED] PwrbOKnown_A
  UVM_INFO @ 3073.407848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_all_wake_ups has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.71481610164908988056138081229698330320912282506216980401991842775651117270074
    Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest/run.log
```
      Offending '(!$isunknown(cio_pwrb_out_o))'
  UVM_ERROR @ 3251.601384 us: (sysrst_ctrl.sv:368) [ASSERT FAILED] PwrbOKnown_A
  UVM_INFO @ 3251.601384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_random_sleep_all_wake_ups has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.31357383811051660240387173699467938629997327725699547000962527956421357703015
    Line 387, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log
```
      Offending '(!$isunknown(cio_pwrb_out_o))'
  UVM_ERROR @ 2922.794798 us: (sysrst_ctrl.sv:368) [ASSERT FAILED] PwrbOKnown_A
  UVM_INFO @ 2922.794798 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '$stable(key_data_i)' has 4 failures:
- Test chip_sw_keymgr_key_derivation has 1 failures.
  - 0.chip_sw_keymgr_key_derivation.52488172167554003818060765651115951728145193265099271445179330490297194700074
    Line 420, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation/latest/run.log
```
      Offending '$stable(key_data_i)'
  UVM_ERROR @ 9864.175895 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
  UVM_INFO @ 9864.175895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_key_derivation_prod has 1 failures.
  - 0.chip_sw_keymgr_key_derivation_prod.85590080655961636566274687018382824596495161811505712097448655169311305649938
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_prod/latest/run.log
```
      Offending '$stable(key_data_i)'
  UVM_ERROR @ 12996.042448 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
  UVM_INFO @ 12996.042448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_key_derivation_jitter_en.105435338615676859798432533479977950664849491274833043607456171706760790114008
    Line 425, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
```
      Offending '$stable(key_data_i)'
  UVM_ERROR @ 11972.314481 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
  UVM_INFO @ 11972.314481 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_key_derivation_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.9022019521015960693043621250530480436815137813496287593159144933206775604139
    Line 413, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
```
      Offending '$stable(key_data_i)'
  UVM_ERROR @ 10001.935152 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
  UVM_INFO @ 10001.935152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:* = ErrorError has 3 failures:
- Test chip_sw_sram_ctrl_scrambled_access has 1 failures.
  - 0.chip_sw_sram_ctrl_scrambled_access.89758389105915223653203941520794123256573831313920758816409767814264749963974
    Line 392, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest/run.log
```
  UVM_ERROR @ 5363.875488 us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 5363.875488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_sram_ctrl_scrambled_access_jitter_en has 1 failures.
  - 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.109377909017133346377945519745775884467338424385060000140903009046390152345666
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest/run.log
```
  UVM_ERROR @ 5660.942757 us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 5660.942757 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.20397860688218218777769189837153699986663616680918189103293782382993735706726
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest/run.log
```
  UVM_ERROR @ 6763.693691 us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 6763.693691 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.69196418371473583446637150405992627154668202858412617697903209350217714889484
    Line 490, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.85640145668866625251839395918108277501845835127822385213375766011821731417457
    Line 501, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.39760201873700775681660688392014873803822796131568231784170466703953218861799
    Line 541, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInWfi, TIMEOUT = * ns has 2 failures:
- Test chip_sw_flash_ctrl_lc_rw_en has 1 failures.
  - 0.chip_sw_flash_ctrl_lc_rw_en.28804564997272213026500690481447315455611338120921519938102266507372312592834
    Line 590, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 12018.666985 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInWfi, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.666985 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_sram_ctrl_execution_main has 1 failures.
  - 0.chip_sw_sram_ctrl_execution_main.58045706252777081565531948375575962094468105540667191451791667175723655857438
    Line 387, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_ERROR @ 12026.891173 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInWfi, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.891173 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 2 failures:
- Test chip_sw_flash_init has 1 failures.
  - 0.chip_sw_flash_init.35955412067729777957505601204746556908243220998580240071047146099544248656484
    Line 334, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_init/latest/run.log
```
  UVM_ERROR @ 2769.662975 us: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x52) != exp (0x4)
  UVM_INFO @ 2769.662975 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_flash_init_reduced_freq has 1 failures.
  - 0.chip_sw_flash_init_reduced_freq.63777125592684463717527724270165922582857932485490379616713489304983655479645
    Line 332, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_init_reduced_freq/latest/run.log
```
  UVM_ERROR @ 2237.980116 us: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2b) != exp (0x7d)
  UVM_INFO @ 2237.980116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.78995780006985019617417759692838600611085739014707162192966319510107248571996
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.167s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.45131663920610852627263410502104459922074421181959491369060881015908749081179
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.174s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.39274992858666966228247705423408301048541639528344830187727697049413339591470
    Line 577, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.60724768116527334882752272747291585087715353640979907463472822967987770543138
    Line 561, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.183047296264627606623282813566827571279949372740593586357089159748103146349
    Line 616, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.54603469857750925528248283028433961553414213962312761601151548531382522074044
    Line 542, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@59208) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.70485401845227287930042901842026049294384917528255503424898793717306436368746
Line 517, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  UVM_ERROR @ 2829.389958 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@59208) { a_addr: 'h0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h4  a_user: 'h247aa  d_param: 'h0  d_source: 'h0  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2829.389958 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_rma_unlocked_test_sim_dv(sw/device/tests/sim_dv/flash_rma_unlocked_test.c:148)] CHECK-fail: curr_state == kSrcLcState has 1 failures:
- Test chip_sw_flash_rma_unlocked has 1 failures.
  - 0.chip_sw_flash_rma_unlocked.31974456279492099247899402699676637402993780469362811071449306537559576436427
    Line 335, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_ERROR @ 2623.243135 us: (sw_logger_if.sv:526) [flash_rma_unlocked_test_sim_dv(sw/device/tests/sim_dv/flash_rma_unlocked_test.c:148)] CHECK-fail: curr_state == kSrcLcState
  UVM_INFO @ 2623.243135 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_ctrl_transition_test_sim_dv(sw/device/tests/sim_dv/lc_ctrl_transition_impl.c:107)] CHECK-fail: State transition failed! has 1 failures:
- Test chip_sw_lc_ctrl_transition has 1 failures.
  - 0.chip_sw_lc_ctrl_transition.46363829218371421149820624692998436807998578237822444908476601498375833936803
    Line 419, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest/run.log
```
  UVM_ERROR @ 3256.241539 us: (sw_logger_if.sv:526) [lc_ctrl_transition_test_sim_dv(sw/device/tests/sim_dv/lc_ctrl_transition_impl.c:107)] CHECK-fail: State transition failed!
  UVM_INFO @ 3256.241539 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@87452) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.77367270747968441572870624460231304472945820918185867322503439417963171508762
Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4228.873440 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@87452) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4228.873440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [adc_ctrl_sleep_debug_cable_wakeup_test_sim_dv(sw/device/tests/sim_dv/adc_ctrl_sleep_debug_cable_wakeup_test.c:60)] DIF-fail: dif_adc_ctrl_configure( adc_ctrl, (dif_adc_ctrl_config_t){ .mode = kDifAdcCtrlLowPowerScanMode, .num_low_power_samples = kNumLowPowerSamples, .num_normal_power_samples = kNumNormalPowerSamples, .power_up_time_aon_cycles = kPowerUpTimeAonCycles, .wake_up_time_aon_cycles = kWakeUpTimeAonCycles}) returns * has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.103688308851836136446343216408540321157900128666143323959992791397756089431490
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 2565.377598 us: (sw_logger_if.sv:526) [adc_ctrl_sleep_debug_cable_wakeup_test_sim_dv(sw/device/tests/sim_dv/adc_ctrl_sleep_debug_cable_wakeup_test.c:60)] DIF-fail: dif_adc_ctrl_configure( adc_ctrl, (dif_adc_ctrl_config_t){ .mode = kDifAdcCtrlLowPowerScanMode, .num_low_power_samples = kNumLowPowerSamples, .num_normal_power_samples = kNumNormalPowerSamples, .power_up_time_aon_cycles = kPowerUpTimeAonCycles, .wake_up_time_aon_cycles = kWakeUpTimeAonCycles}) returns 3
  UVM_INFO @ 2565.377598 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otbn_mem_scramble_test_sim_dv(sw/device/tests/otbn_mem_scramble_test.c:248)] CHECK-fail: Expecting at least * IMEM integrity errors, got * has 1 failures:
- Test chip_sw_otbn_mem_scramble has 1 failures.
  - 0.chip_sw_otbn_mem_scramble.22239334070333503530622049307745832523686492828934299216173895047253064584606
    Line 387, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_mem_scramble/latest/run.log
```
  UVM_ERROR @ 3618.568848 us: (sw_logger_if.sv:526) [otbn_mem_scramble_test_sim_dv(sw/device/tests/otbn_mem_scramble_test.c:248)] CHECK-fail: Expecting at least 48 IMEM integrity errors, got 47
  UVM_INFO @ 3618.568848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.47806899122672347296835909982808173578804258943089927374822106754663302990812
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2923.776865 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 2923.776865 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.95989706349180249925554576835193701086907069781239843031180755882812367661038
    Line 385, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3352.923886 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3352.923886 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_pings_test_sim_dv(sw/device/tests/alert_handler_lpg_sleep_mode_pings.c:408)] CHECK-fail: Phase #*: No new alerts has been fired after wakeup! has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.69469459075228729538341529139770625018099770898352988286916888121631779197505
    Line 403, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  UVM_ERROR @ 8648.735762 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_pings_test_sim_dv(sw/device/tests/alert_handler_lpg_sleep_mode_pings.c:408)] CHECK-fail: Phase #2: No new alerts has been fired after wakeup!
  UVM_INFO @ 8648.735762 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [csrng_fuse_en_sw_app_read_sim_dv(sw/device/tests/sim_dv/csrng_fuse_en_sw_app_read.c:86)] CHECK-fail: fw_enable not expected (*) has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.69519860900926475552969805171140078699046867892899630343095930225725312014268
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 4136.761118 us: (sw_logger_if.sv:526) [csrng_fuse_en_sw_app_read_sim_dv(sw/device/tests/sim_dv/csrng_fuse_en_sw_app_read.c:86)] CHECK-fail: `fw_enable` not expected (96)
  UVM_INFO @ 4136.761118 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.15106289222602806935060494161221765765164706679005043823649630710698064581849
    Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2601.270172 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2601.270172 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_external_clk_src_for_lc_test_sim_dv(sw/device/tests/sim_dv/lc_ctrl_transition_impl.c:107)] CHECK-fail: State transition failed! has 1 failures:
- Test chip_sw_clkmgr_external_clk_src_for_lc has 1 failures.
  - 0.chip_sw_clkmgr_external_clk_src_for_lc.115568119674147051256481817167984899946581910957476662428128283595337049209490
    Line 385, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_lc/latest/run.log
```
  UVM_ERROR @ 2750.088984 us: (sw_logger_if.sv:526) [clkmgr_external_clk_src_for_lc_test_sim_dv(sw/device/tests/sim_dv/lc_ctrl_transition_impl.c:107)] CHECK-fail: State transition failed!
  UVM_INFO @ 2750.088984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:232)] DIF-fail: dif_adc_ctrl_configure( adc_ctrl, (dif_adc_ctrl_config_t){ .mode = kDifAdcCtrlLowPowerScanMode, .num_low_power_samples = kNumLowPowerSamples, .num_normal_power_samples = kNumNormalPowerSamples, .power_up_time_aon_cycles = (uint8_t)power_up_time_aon_cycles + *, .wake_up_time_aon_cycles = wake_up_time_aon_cycles}) returns * has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.80017844862340400103271760043753126460108843180892529124489129739347468315448
    Line 386, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 8074.776845 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:232)] DIF-fail: dif_adc_ctrl_configure( adc_ctrl, (dif_adc_ctrl_config_t){ .mode = kDifAdcCtrlLowPowerScanMode, .num_low_power_samples = kNumLowPowerSamples, .num_normal_power_samples = kNumNormalPowerSamples, .power_up_time_aon_cycles = (uint8_t)power_up_time_aon_cycles + 1, .wake_up_time_aon_cycles = wake_up_time_aon_cycles}) returns 3
  UVM_INFO @ 8074.776845 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.73856008399217249309872177377551490066022761158096506218670134305588905567117
    Line 470, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.24628372067140159756806047079835651944273211685012080936564339508966398815764
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```