ADC_CTRL Simulation Results

Monday September 01 2025 16:38:37 UTC

GitHub Revision: 9bb489f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	11.010s	5.927ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.980s	1.141ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.270s	480.339us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	30.050s	51.198ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	1.920s	585.221us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.820s	390.498us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.270s	480.339us	1	1	100.00
		adc_ctrl_csr_aliasing	1.920s	585.221us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	3.383m	492.776ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	4.806m	329.130ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.497m	162.960ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	3.803m	490.423ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.971m	357.992ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	4.768m	617.002ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	3.974m	569.865ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	8.800m	359.253ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.280s	3.158ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	16.530s	35.227ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	47.360s	81.193ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	12.302m	421.803ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.130s	380.307us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.100s	466.608us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.540s	477.955us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.540s	477.955us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.980s	1.141ms	1	1	100.00
		adc_ctrl_csr_rw	1.270s	480.339us	1	1	100.00
		adc_ctrl_csr_aliasing	1.920s	585.221us	1	1	100.00
		adc_ctrl_same_csr_outstanding	7.940s	4.606ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.980s	1.141ms	1	1	100.00
		adc_ctrl_csr_rw	1.270s	480.339us	1	1	100.00
		adc_ctrl_csr_aliasing	1.920s	585.221us	1	1	100.00
		adc_ctrl_same_csr_outstanding	7.940s	4.606ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	1.570s	4.386ms	1	1	100.00
		adc_ctrl_tl_intg_err	9.450s	4.067ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	9.450s	4.067ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.740s	2.606ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00