EDN Simulation Results

Monday September 01 2025 16:38:37 UTC

GitHub Revision: 9bb489f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.860s 31.402us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.250s 37.717us 1 1 100.00
V1 csr_rw edn_csr_rw 0.910s 20.740us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.500s 174.475us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.160s 103.884us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.080s 20.585us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.910s 20.740us 1 1 100.00
edn_csr_aliasing 1.160s 103.884us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.880s 85.920us 1 1 100.00
V2 csrng_commands edn_genbits 1.880s 85.920us 1 1 100.00
V2 genbits edn_genbits 1.880s 85.920us 1 1 100.00
V2 interrupts edn_intr 1.110s 35.910us 1 1 100.00
V2 alerts edn_alert 1.000s 28.005us 1 1 100.00
V2 errs edn_err 1.090s 36.866us 1 1 100.00
V2 disable edn_disable 0.950s 12.512us 1 1 100.00
edn_disable_auto_req_mode 1.530s 37.748us 1 1 100.00
V2 stress_all edn_stress_all 1.400s 121.333us 1 1 100.00
V2 intr_test edn_intr_test 0.880s 11.087us 1 1 100.00
V2 alert_test edn_alert_test 1.140s 34.652us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 1.780s 53.568us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 1.780s 53.568us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.250s 37.717us 1 1 100.00
edn_csr_rw 0.910s 20.740us 1 1 100.00
edn_csr_aliasing 1.160s 103.884us 1 1 100.00
edn_same_csr_outstanding 1.080s 120.189us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.250s 37.717us 1 1 100.00
edn_csr_rw 0.910s 20.740us 1 1 100.00
edn_csr_aliasing 1.160s 103.884us 1 1 100.00
edn_same_csr_outstanding 1.080s 120.189us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 5.020s 567.745us 1 1 100.00
edn_tl_intg_err 2.280s 105.758us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.890s 40.984us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.000s 28.005us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 5.020s 567.745us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 5.020s 567.745us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 5.020s 567.745us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 5.020s 567.745us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.000s 28.005us 1 1 100.00
edn_sec_cm 5.020s 567.745us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.000s 28.005us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.280s 105.758us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets