ENTROPY_SRC/RNG_4BITS Simulation Results

Monday September 01 2025 16:38:37 UTC

GitHub Revision: 9bb489f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	entropy_src_smoke	3.000s	111.934us	1	1	100.00
V1	csr_hw_reset	entropy_src_csr_hw_reset	4.000s	30.478us	1	1	100.00
V1	csr_rw	entropy_src_csr_rw	3.000s	79.662us	1	1	100.00
V1	csr_bit_bash	entropy_src_csr_bit_bash	7.000s	260.128us	1	1	100.00
V1	csr_aliasing	entropy_src_csr_aliasing	4.000s	47.550us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	entropy_src_csr_mem_rw_with_rand_reset	3.000s	156.284us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	entropy_src_csr_rw	3.000s	79.662us	1	1	100.00
		entropy_src_csr_aliasing	4.000s	47.550us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	entropy_src_smoke	3.000s	111.934us	1	1	100.00
		entropy_src_rng	5.200m	17.091ms	1	1	100.00
		entropy_src_fw_ov	2.033m	6.881ms	0	1	0.00
V2	firmware_mode	entropy_src_fw_ov	2.033m	6.881ms	0	1	0.00
V2	rng_mode	entropy_src_rng	5.200m	17.091ms	1	1	100.00
V2	rng_max_rate	entropy_src_rng_max_rate	4.483m	16.030ms	1	1	100.00
V2	health_checks	entropy_src_rng	5.200m	17.091ms	1	1	100.00
V2	conditioning	entropy_src_rng	5.200m	17.091ms	1	1	100.00
V2	interrupts	entropy_src_rng	5.200m	17.091ms	1	1	100.00
		entropy_src_intr	5.000s	55.098us	1	1	100.00
V2	alerts	entropy_src_rng	5.200m	17.091ms	1	1	100.00
		entropy_src_functional_alerts	6.000s	245.324us	1	1	100.00
V2	stress_all	entropy_src_stress_all	4.000s	56.532us	1	1	100.00
V2	functional_errors	entropy_src_functional_errors	4.000s	109.363us	1	1	100.00
V2	firmware_ov_read_contiguous_data	entropy_src_fw_ov_contiguous	7.000s	1.013ms	1	1	100.00
V2	intr_test	entropy_src_intr_test	3.000s	113.119us	1	1	100.00
V2	alert_test	entropy_src_alert_test	3.000s	52.942us	1	1	100.00
V2	tl_d_oob_addr_access	entropy_src_tl_errors	5.000s	222.119us	1	1	100.00
V2	tl_d_illegal_access	entropy_src_tl_errors	5.000s	222.119us	1	1	100.00
V2	tl_d_outstanding_access	entropy_src_csr_hw_reset	4.000s	30.478us	1	1	100.00
		entropy_src_csr_rw	3.000s	79.662us	1	1	100.00
		entropy_src_csr_aliasing	4.000s	47.550us	1	1	100.00
		entropy_src_same_csr_outstanding	4.000s	85.447us	1	1	100.00
V2	tl_d_partial_access	entropy_src_csr_hw_reset	4.000s	30.478us	1	1	100.00
		entropy_src_csr_rw	3.000s	79.662us	1	1	100.00
		entropy_src_csr_aliasing	4.000s	47.550us	1	1	100.00
		entropy_src_same_csr_outstanding	4.000s	85.447us	1	1	100.00
V2		TOTAL			11	12	91.67
V2S	tl_intg_err	entropy_src_sec_cm	4.000s	98.378us	1	1	100.00
		entropy_src_tl_intg_err	4.000s	65.829us	1	1	100.00
V2S	sec_cm_config_regwen	entropy_src_rng	5.200m	17.091ms	1	1	100.00
		entropy_src_cfg_regwen	3.000s	77.640us	1	1	100.00
V2S	sec_cm_config_mubi	entropy_src_rng	5.200m	17.091ms	1	1	100.00
V2S	sec_cm_config_redun	entropy_src_rng	5.200m	17.091ms	1	1	100.00
V2S	sec_cm_intersig_mubi	entropy_src_rng	5.200m	17.091ms	1	1	100.00
		entropy_src_fw_ov	2.033m	6.881ms	0	1	0.00
V2S	sec_cm_main_sm_fsm_sparse	entropy_src_functional_errors	4.000s	109.363us	1	1	100.00
		entropy_src_sec_cm	4.000s	98.378us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	entropy_src_functional_errors	4.000s	109.363us	1	1	100.00
		entropy_src_sec_cm	4.000s	98.378us	1	1	100.00
V2S	sec_cm_rng_bkgn_chk	entropy_src_rng	5.200m	17.091ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	entropy_src_functional_errors	4.000s	109.363us	1	1	100.00
		entropy_src_sec_cm	4.000s	98.378us	1	1	100.00
V2S	sec_cm_ctr_redun	entropy_src_functional_errors	4.000s	109.363us	1	1	100.00
		entropy_src_sec_cm	4.000s	98.378us	1	1	100.00
V2S	sec_cm_ctr_local_esc	entropy_src_functional_errors	4.000s	109.363us	1	1	100.00
V2S	sec_cm_esfinal_rdata_bus_consistency	entropy_src_functional_alerts	6.000s	245.324us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	entropy_src_tl_intg_err	4.000s	65.829us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	external_health_tests	entropy_src_rng_with_xht_rsps	50.000s	17.104ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	22	95.45

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_alert triggered unexpectedly has 1 failures:
  • Test entropy_src_fw_ov has 1 failures.

    • 0.entropy_src_fw_ov.43235974414666854796296994111550293937541988541212288811447852967108605335858
      Line 862, in log /nightly/current_run/scratch/master/entropy_src-sim-xcelium/0.entropy_src_fw_ov/latest/run.log

        UVM_ERROR @ 6881275654 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_alert triggered unexpectedly
        UVM_INFO @ 6881275654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---